HT48F70E datasheet(13/58 Pages) HOLTEK

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HT48F70E

Rev. 1.30

July 29, 2009

Bank Pointer

- BP

The RAM Data Memory is divided into two Banks,

known as Bank 0 and Bank 1. With the exception of the

EECR register, all of the Special Purpose Registers and

General Purpose Registers are contained in Bank 0.

Bank 1 contains only one register, which is the

EEPROM Control Register, known as EECR. Selecting

the required Data Memory area is achieved using the

Bank Pointer. If data in Bank 0 is to be accessed, then

the BP register must be loaded with the value

²00²,

while if data in Bank 1 is to be accessed, then the BP

²01².

Using Memory Pointer MP0 and Indirect Addressing

spective of the value of the Bank Pointer. The EECR

can only be accessed indirectly using memory pointer

MP1 and the indirect addressing register, IAR1, after the

BP register has first been loaded with the value

²01².

Data can only be read from or written to the EEPROM

via this register.

The Data Memory is initialised to Bank 0 after a reset,

except for the WDT time-out reset in the Power Down

Mode, in which case, the Data Memory bank remains

unaffected. It should be noted that Special Function

Data Memory is not affected by the bank selection,

which means that the Special Function Registers can be

accessed from within either Bank 0 or Bank 1. Directly

addressing the Data Memory will always result in Bank 0

being accessed irrespective of the value of the Bank

Pointer.

Accumulator

- ACC

The Accumulator is central to the operation of any

microcontroller and is closely related with operations

carried out by the ALU. The Accumulator is the place

where all intermediate results from the ALU are stored.

Without the Accumulator it would be necessary to write

the result of each calculation or logical operation such

as addition, subtraction, shift, etc., to the Data Memory

resulting in higher programming and timing overheads.

Data transfer operations usually involve the temporary

storage function of the Accumulator; for example, when

transferring data between one user defined register and

another, it is necessary to do this by passing the data

through the Accumulator as no direct transfer between

two registers is permitted.

Program Counter Low Register

- PCL

To provide additional program control functions, the low

byte of the Program Counter is made accessible to pro-

grammers by locating it within the Special Purpose area

of the Data Memory. By manipulating this register, direct

jumps to other program locations are easily imple-

mented. Loading a value directly into this PCL register

will cause a jump to the specified Program Memory lo-

cation, however, as the register is only 8-bit wide, only

jumps within the current Program Memory page are per-

mitted. When such operations are used, note that a

dummy cycle will be inserted.

Look-up Table Registers

- TBLP, TBLH

These two special function registers are used to control

operation of the look-up table which is stored in the Pro-

gram Memory. TBLP is the table pointer and indicates

the location where the table data is located. Its value

must be setup before any table read commands are ex-

ecuted. Its value can be changed, for example using the

²INC² or ²DEC² instructions, allowing for easy table data

pointing and reading. TBLH is the location where the

high order byte of the table data is stored after a table

read data instruction has been executed. Note that the

lower order table data byte is transferred to a user de-

fined location.

Watchdog Timer Register

- WDTS

The Watchdog feature of the microcontroller provides

an automatic reset function giving the microcontroller a

means of protection against spurious jumps to incorrect

Program Memory addresses. To implement this, a timer

is provided within the microcontroller which will issue a

reset command when its value overflows. To provide

variable Watchdog Timer reset times, the Watchdog

Timer clock source can be divided by various division ra-

tios, the value of which is set using the WDTS register.

By writing directly to this register, the appropriate divi-

sion ratio for the Watchdog Timer clock source can be

setup. Note that only the lower 3 bits are used to set divi-

sion ratios between 1 and 128.

B a n k P o i n t e r

b 7

b 0

B P 0

D a t a M e m o r y

B a n k 0

B a n k 1

N o t u s e d , m u s t b e r e s e t t o " 0 "

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