HT46R064 datasheet(39/99 Pages) HOLTEK

39 / 99 page

HT46R064/065/066/0662/067

Rev. 1.10

June 9, 2009

· PFD Output

The PFD function output is pin-shared with an I/O pin.

The output function of this pin is chosen using the

CTRL0 register. Note that the corresponding bit of

the port control register, must setup the pin as an

output to enable the PFD output. If the port control

function as a normal logic input with the usual

pull-high selection, even if the PFD function has been

selected.

· PWM Outputs

The PWM function whose outputs are pin-shared with

I/O pins. The PWM output functions are chosen using

the CTRL0 and CTRL2 registers. Note that the corre-

sponding bit of the port control registers, for the output

pin, must setup the pin as an output to enable the

PWM output. If the pins are setup as inputs, then the

pin will function as a normal logic input with the usual

pull-high selections, even if the PWM registers have

enabled the PWM function.

· SCOM Driver Pins

Pins PB0~PB3 on Port B can be used as LCD COM

driver pins. This function is controlled using the

SCOMC register which will generate the necessary

1/2 bias signals on these four pins.

· A/D Inputs

Each device in this series has either four or eight in-

puts to the A/D converter. All of these analog inputs

are pin-shared with I/O pins. If these pins are to be

used as A/D inputs and not as I/O pins then the corre-

sponding PCRn bits in the A/D converter control regis-

ter, ADCR, must be properly setup. There are no

configuration options associated with the A/D con-

verter. If chosen as I/O pins, then full pull-high resistor

configuration options remain, however if used as A/D

inputs then any pull-high resistor configuration options

associated with these pins will be automatically dis-

connected.

Pin Remapping Configuration

HT46R066/HT46R0662/HT46R067

The pin remapping function enables the function pins

INT, TC0 and PFD to be located on different port pins. It

is important not to confuse the Pin Remapping function

with the Pin-shared function, these two functions have

no interdependence.

The PCFG bit in the CTRL0 register allows the three

function pins INT, TC0 and PFD to be remapped to dif-

ferent port pins. After power up, this bit will be reset to

zero, which will define the default port pins to which

these three functions will be mapped. Changing this bit

will move the functions to other port pins.

Examination of the pin names on the package diagrams

will reveal that some pin function names are repeated,

this indicates a function pin that can be remapped to

other port pins. If the pin name is bracketed then this in-

dicates its alternative location. Pin names without brack-

ets indicates its default location which is the condition

after Power-on.

PCFG Bit Status

PCFG Bit

Pin Mapping

INT/PA3

TC0/PA2

PFD/PA1

[INT]/PB5

[TC0]/PB4

[PFD]/PB3

Pin Remapping

I/O Pin Structures

The diagrams illustrate the I/O pin internal structures. As

the exact logical construction of the I/O pin may differ

from these drawings, they are supplied as a guide only

to assist with the functional understanding of the I/O

pins.

V D D

W a k e - u p S e l e c t

S y s t e m W a k e - u p

R e a d D a t a R e g i s t e r

C K

C o n t r o l B i t

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

D a t a B i t

I / O p i n

P A o n l y

W e a k

P u l l - u p

P u l l - H i g h

S e l e c t

Generic Input/Output Ports

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