MPC5604PEFMLL datasheet(61/84 Pages) FREESCALE

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MPC5604P Microcontroller Data Sheet, Rev. 5

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

3.16.2

IEEE 1149.1 interface timing

Ttr

CC D Output transition time

output pin4

MEDIUM configuration

CL = 25pF,

VDD = 5.0 V ± 10%, PAD3V5V = 0

—

CL = 50pF,

VDD = 5.0 V ± 10%, PAD3V5V = 0

——

CL = 100pF,

VDD = 5.0 V ± 10%, PAD3V5V = 0

——

CL = 25pF,

VDD = 3.3 V ± 10%, PAD3V5V = 1

——

CL = 50pF,

VDD = 3.3 V ± 10%, PAD3V5V = 1

——

CL = 100pF,

VDD = 3.3 V ± 10%, PAD3V5V = 1

——

WFRST SR P RESET input filtered

pulse

——

—

WNFRST SR P RESET input not filtered

pulse

—500

—

TPOR

CC D maximum delay before

internal reset is released

after all VDD_HV reach

nominal supply

monotonic VDD_HV supply ramp

—

|IWPU| CC P Weak pull-up current

absolute value

VDD = 3.3 V ± 10%, PAD3V5V = 1

—

150

µA

VDD = 5.0 V ± 10%, PAD3V5V = 0

—

150

VDD = 5.0 V ± 10%, PAD3V5V = 1

—

250

1 V

DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified

2 All values need to be confirmed during device validation.

3 This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of

device reference manual).

4 C

L includes device and package capacitance (CPKG <5pF).

5 The configuration PAD3V5 = 1 when V

DD = 5 V is only transient configuration during power-up. All pads but RESET

and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

Table 35. JTAG pin AC electrical characteristics

No.

Symbol

Parameter

Conditions Min Max Unit

1tJCYC

D TCK cycle time

—

100

—

2tJDC

D TCK clock pulse width (measured at VDD_HV_IOx/2)

—

3tTCKRISE

D TCK rise and fall times (40% - 70%)

—

4tTMSS, tTDIS CC

D TMS, TDI data setup time

—

Table 34. RESET electrical characteristics (continued)

Symbol

Parameter

Conditions1

Value2

Unit

Min

Typ

Max

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