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78P2344JAT датащи(PDF) 2 Page - Teridian Semiconductor Corporation

номер детали 78P2344JAT
подробное описание детали  4-port E3/DS3/STS-1 LIU with Jitter Attenuator
PDF  37 Pages
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производитель  TERIDIAN [Teridian Semiconductor Corporation]
домашняя страница  http://www.teridian.com
Logo TERIDIAN - Teridian Semiconductor Corporation

78P2344JAT датащи(HTML) 2 Page - Teridian Semiconductor Corporation

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78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
Page 2 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
FUNCTIONAL DESCRIPTION
The
78P2344JAT
contains
all
the
necessary
transmit
and
receive
circuitry
for
connection
between E3, DS3, or STS-1 line interfaces and
digital Framer/Mapper ICs.
OPERATING RATE
The Master Control Register (MSCR) determines
which mode the device operates in according to the
table below.
The MSL0 pin is also provided for
mode selection in applications without a serial
control interface. Upon power-up or reset, the state
of the MSL0 pin is sensed and mapped into the DS3
and E3 register bits representing the appropriate
mode of operation. After power-up/reset, the state of
the MSL0 pin is ignored.
Standard
MSL0 pin
DS3 bit
E3 bit
E3
L
0
1
DS3
H
1
0
STS-1
Z
0
0
STS-1
Z
1
1
RECEIVER OPERATION
The receiver input is either transformer-coupled or
capacitor-coupled to the line signal. In applications
where the highest performance and isolation are
required, a 1:1 transformer is used in the receive
path. In applications where isolation is provided
elsewhere in the circuit, capacitor coupling can be
used. The receiver input should be line terminated
externally with a termination resistor.
The AMI signal first enters an AGC, which has a
selectable gain range setting. In normal operation,
the AGC can compensate for signals with up to 6dB
of flat loss.
When Receiver Monitor Mode is
enabled, the AGC can compensate for a DSX3
monitor signal with 16 to 20 dB of flat loss.
The
signal then enters a high performance adaptive
equalizer.
The equalizer is designed to overcome
inter-symbol interference caused by long cable
lengths.
Because the equalizer is adaptive, the
circuit will work with all square-shaped signals such
as DS3-high or 34.368 Mbit/s E3. The variable gain
differential amplifier automatically controls the gain
to
maintain
a
constant
voltage
level
output
regardless of the input voltage level.
The jitter tolerance of 78P2344JAT meets the
requirements of ITU-T G.823 for E3 rates; the
requirements of ITU-T G.824 and Telcordia GR-499
(Cat I and II) for DS3 rates; and the requirements of
Telcordia GR-253 for STS1 rates.
With the Jitter Attenuator disabled, the jitter transfer
function meets the requirements of GR-499 for
Category II DS3 interfaces.
When
the
Jitter
Attenuator
is
enabled,
the
78P2344JAT meets the requirements of GR-499
and
GR-253
for
all
categories
of
DS3/STS1
equipment and the ETSI TBR-24 requirements for
E3 rates.
To check conformance with other
standards,
please
refer
to
the
JITTER
ATTENUATOR TRANSFER FUNCTION section for
more detailed info.
RECEIVER MONITOR MODE
When in monitor mode, 20dB of flat gain is applied
to the incoming signal before it is fed to the receive
equalizer. This mode is controlled by the MON bit in
the Mode Control Register.
SIGNAL DETECT
When the received signal is below a minimum
threshold, the corresponding LOS signal (bit) is
asserted. A time delay is provided before this output
is active so that transient interruptions do not cause
false indications. The LOS signal can also be used
to trigger an interrupt on the INTRx pin when serial
interface control is not available. This is controlled
by setting the RXER bit in the Interrupt Control
Register (INTC).
Note:
In DS3 or STS-1 mode, when LBO is not
enabled, the transmitters have to be properly
terminated to ensure reliable LOS detection.
If a
transmitter is not terminated, the resultant 2x signal
is large enough to couple to the neighboring
receivers through the ESD diodes, causing false
Signal Detect indication.



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