ADE7858ACPZ datasheet(52/76 Pages) AD

52 / 76 page

ADE7858

Preliminary Technical Data

Rev. PrA| Page 52 of 76

Figure 60. I2C Write Operation of a 32 bit register

ACK generated by

Master

slave address

Byte3 (MS) of reg

Byte2 of reg

Byte1of reg

Byte0 (LS) of reg

S 01 11 00 0

MS 8 bits of reg

address

slave address

LS 8 bits of reg

address

ACK generated by

ADE7858

ACK generated by

ADE7858

Figure 61. I2C Read Operation of a 32-bit register

SPI Compatible Interface

The Serial Peripheral Interface (SPI) of the ADE7858 is always

a slave of the communication and consists in four pins: SCLK,

MOSI, MISO and SS . The serial clock for a data transfer is

applied at the SCLK logic input. This logic input has a Schmitt

trigger input structure that allows slow rising (and falling) clock

edges to be used. All data transfer operations are synchronized

to the serial clock. Data is shifted into the ADE7858 at the

MOSI logic input on the falling edge of SCLK and ADE7858

samples it on the rising edge of SCLK. Data is shifted out of the

ADE7858 at the MISO logic output on a falling edge of SCLK

and can be sampled by the master device on the raising edge of

SCLK. The most significant bit of the word is shifted in and out

first. The maximum serial clock frequency supported by this

interface is 2.5MHz. MISO stays in high impedance when no

data is transmitted from the ADE7858. Figure 62 presents

details of the connection between ADE7858 SPI and a master

device containing an SPI interface.

The SS logic input is the chip select input. This input is used

when multiple devices share the serial bus. The SS input

should be driven low for the entire data transfer operation.

Bringing SS high during a data transfer operation aborts the

transfer and places the serial bus in a high impedance state. A

new transfer can then be initiated by bringing the SS logic

input back low. However, because aborting a data transfer

before completion leaves the accessed register in a state that

cannot be guaranteed, every time a register is written, its value

should be verified by reading it back.

ADE7858

MOSI

SCLK

SS\

SPI

device

MOSI

SCK

SS\

MISO

Figure 62. Connecting ADE7858 SPI with an SPI device

The protocol is similar to the protocol used in I2C interface.

SPI Read Operation

The read operation using the SPI interface of the ADE7858

initiates when the master sets SS pin low and begins sending

one byte representing the address of the ADE7858 on the

MOSI line. The master sets data on the MOSI line starting with

the first high to low transition of SCLK. The SPI of the

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