TAS5713 datasheet(22/63 Pages) TI

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TAS5713

SLOS637 – DECEMBER 2009

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DETAILED DESCRIPTION

POWER SUPPLY

To facilitate system design, the TAS5713 needs only a 3.3-V supply in addition to the (typical) 18-V power-stage

supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all

circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap

circuitry requiring only a few external capacitors.

In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is

designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins

(BST_x), and power-stage supply pins (PVDD_x). The gate-drive voltage (GVDD_OUT) is derived from the

PVDD voltage. Special attention should be paid to placing all decoupling capacitors as close to their associated

pins as possible. Inductance between the power-supply pins and decoupling capacitors must be avoided.

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin

(BST_x) to the power-stage output pin (OUT_x). When the power-stage output is low, the bootstrap capacitor is

charged through an internal diode connected between the gate-drive regulator output pin (GVDD_OUT) and the

bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output

potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM

switching frequencies in the range from 352 kHz to 384 kHz, it is recommended to use 33-nF, X7R ceramic

capacitors, size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage,

even during minimal PWM duty cycles, to keep the high-side power-stage FET (LDMOS) fully turned on during

the remaining part of the PWM cycle.

Special attention should be paid to the power-stage power supply; this includes component selection, PCB

placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_x). For

optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_x pin is

decoupled with a 100-nF, X7R ceramic capacitor placed as close as possible to each supply pin.

The TAS5713 is fully protected against erroneous power-stage turnon due to parasitic gate charging.

2C CHIP SELECT

A_SEL_FAULT is an input pin during power up. It can be pulled high (15-k

Ω pullup) or low (15-kΩ pulldown).

High indicates an I2C subaddress of 0x36, and low a subaddress of 0x34.

I2C Device Address Change Procedure

•

Write to device address change enable register, 0xF8 with a value of 0xF9 A5 A5 A5.

•

Write to device register 0xF9 with a value of 0x0000 00XX, where XX is the new address.

•

Any writes after that should use the new device address XX.

SINGLE-FILTER PBTL MODE

The TAS5713 supports parallel BTL (PBTL) mode with OUT_A/OUT_B (and OUT_C/OUT_D) connected before

the LC filter. In order to put the part in PBTL configuration, drive PBTL (pin 8) HIGH. This synchronizes the

turnoff of half-bridges A and B (and similarly C/D) if an overcurrent condition is detected in either half-bridge.

There is a pulldown resistor on the PBTL pin that configures the part in BTL mode if the pin is left floating.

PWM output multiplexers should be updated to set the device in PBTL mode. Output Mux Register (0x25) should

be written with a value of 0x01 10 32 45. Also, the PWM shutdown register (0x19) should be written with a value

of 0x3A.

DEVICE PROTECTION SYSTEM

Overcurrent (OC) Protection With Current Limiting

The device has independent, fast-reacting current detectors on all high-side and low-side power-stage FETs. The

detector outputs are closely monitored by two protection systems. The first protection system controls the power

stage in order to prevent the output current further increasing, i.e., it performs a cycle-by-cycle current-limiting

function, rather than prematurely shutting down during combinations of high-level music transients and extreme

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