ATXMEGA64A1 datasheet(23/99 Pages) ATMEL

23 / 99 page

8067I–AVR–04/09

XMEGA A1

12. System Control and Reset

12.1

Features

• Multiple reset sources for safe operation and device reset

– Power-On Reset

– External Reset

– Watchdog Reset

The Watchdog Timer runs from separate, dedicated oscillator

– Brown-Out Reset

Accurate, programmable Brown-Out levels

– JTAG Reset

– PDI reset

– Software reset

• Asynchronous reset

– No running clock in the device is required for reset

• Reset status register

12.2

Resetting the AVR

During reset, all I/O registers are set to their initial values. The SRAM content is not reset. Appli-

cation execution starts from the Reset Vector. The instruction placed at the Reset Vector should

be an Absolute Jump (JMP) instruction to the reset handling routine. By default the Reset Vector

address is the lowest Flash program memory address, ‘0’, but it is possible to move the Reset

Vector to the first address in the Boot Section.

The I/O ports of the AVR are immediately tri-stated when a reset source goes active.

The reset functionality is asynchronous, so no running clock is required to reset the device.

After the device is reset, the reset source can be determined by the application by reading the

Reset Status Register.

12.3

Reset Sources

12.3.1

Power-On Reset

The MCU is reset when the supply voltage VCC is below the Power-on Reset threshold voltage.

12.3.2

External Reset

The MCU is reset when a low level is present on the RESET pin.

12.3.3

Watchdog Reset

The MCU is reset when the Watchdog Timer period expires and the Watchdog Reset is enabled.

The Watchdog Timer runs from a dedicated oscillator independent of the System Clock. For

more details see “WDT - Watchdog Timer” on page 24.

12.3.4

Brown-Out Reset

The MCU is reset when the supply voltage VCC is below the Brown-Out Reset threshold voltage

and the Brown-out Detector is enabled. The Brown-out threshold voltage is programmable.

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