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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATtiny88 датащи(PDF) 208 Page - ATMEL Corporation |
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ATtiny88 датащи(HTML) 208 Page - ATMEL Corporation |
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208 / 266 page  208 8008C–AVR–03/09 ATtiny48/88 4. fCK = CPU clock frequency 5. This requirement applies to all 2-wire serial interface operation in ATtiny48/88. Other devices connected to the 2-wire serial bus need only obey the general f SCL requirement. 6. The actual low period generated by the 2-wire serial interface of ATtiny48/88 is (1/fSCL - 2/fCK), thus fCK must be greater than 6 MHz for the low time requirement to be strictly met at f SCL = 100 kHz. 7. The actual low period generated by the 2-wire serial interface of ATtiny48/88 is (1/f SCL - 2/fCK), thus the low time requirement will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATtiny48/88 devices connected to the bus may communi- cate at full speed (400 kHz) with other ATtiny48/88 devices, as well as any other device with a proper t LOW acceptance margin. Figure 21-3. 2-wire Serial Bus Timing tSU;STA tLOW tHIGH tLOW tof tHD;STA tHD;DAT tSU;DAT tSU;STO tBUF SCL SDA tr |
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