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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATtiny88 датащи(PDF) 197 Page - ATMEL Corporation |
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ATtiny88 датащи(HTML) 197 Page - ATMEL Corporation |
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197 / 266 page  197 8008C–AVR–03/09 ATtiny48/88 Figure 20-7. Serial Programming and Verify (1) Notes: 1. If the device is clocked by the internal oscillator, it is no need to connect a clock source to the CLKI pin. 2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8 – 5.5V When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into 0xFF. Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low:> 2 CPU clock cycles for f ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz High:> 2 CPU clock cycles for f ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz 20.8.1 Serial Programming Pin Mapping VCC GND CLKI SCK MISO MOSI RESET +1.8 - 5.5V AVCC +1.8 - 5.5V (2) Table 20-13. Pin Mapping Serial Programming Symbol Pins I/O Description MOSI PB3 I Serial Data in MISO PB4 O Serial Data out SCK PB5 I Serial Clock |
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