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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATtiny88 датащи(PDF) 123 Page - ATMEL Corporation |
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ATtiny88 датащи(HTML) 123 Page - ATMEL Corporation |
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123 / 266 page  123 8008C–AVR–03/09 ATtiny48/88 • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see Table 14-5). This means that the minimum SCK period will be two CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f osc/4 or lower. The SPI interface on the ATtiny48/88 is also used for program memory and EEPROM down- loading or uploading. See page 196 for serial programming and verification. 14.5.3 SPDR – SPI Data Register The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. Bit 765 43210 MSB LSB SPDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value XXXXXXX X Undefined |
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