6

AT60142HT

7841A–AERO–10/09

Data Retention Mode

Atmel CMOS RAM's are designed with battery backup in mind. Data retention voltage

and supply current are guaranteed over temperature. The following rules insure data

retention:

2. Output Enable (OE) should be held high to keep the RAM outputs high imped-

ance, minimizing power dissipation.

3. During power-up and power-down transitions CS and OE must be kept between

voltages (3V).

Figure 1. Data Retention Timing

Data Retention Characteristics

Parameter Description

Min

Unit

2.0

–

–

V

Chip deselect to data retention time

0.0

–

–

ns

Operation recovery time

––

ns

(2)

Data retention current

–

0.700

1.5

(AT60142HT-15)

mA

1.5

(AT60142HT-17)

1.

2.