ATmega32U2 datasheet(136/314 Pages) ATMEL

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7799B–AVR–07/09

ATmega8U2/16U2/32U2

• Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt

Vector (See “Interrupts” on page 64.) is executed when the ICFn Flag, located in TIFRn, is set.

Bit 3 – OCIEnC: Timer/Countern, Output Compare C Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The corresponding

Interrupt Vector (See “Interrupts” on page 64.) is executed when the OCFnC Flag, located in

TIFRn, is set.

• Bit 2 – OCIEnB: Timer/Countern, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The corresponding

Interrupt Vector (See “Interrupts” on page 64.) is executed when the OCFnB Flag, located in

TIFRn, is set.

• Bit 1 – OCIEnA: Timer/Countern, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Countern Output Compare A Match interrupt is enabled. The corresponding

Interrupt Vector (See “Interrupts” on page 64.) is executed when the OCFnA Flag, located in

TIFRn, is set.

• Bit 0 – TOIEn: Timer/Countern, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Countern Overflow interrupt is enabled. The corresponding Interrupt Vector

(See “Interrupts” on page 64.) is executed when the TOVn Flag, located in TIFRn, is set.

16.11.10 TIFR1 – Timer/Counter1 Interrupt Flag Register

• Bit 5 – ICFn: Timer/Countern, Input Capture Flag

This flag is set when a capture event occurs on the ICPn pin. When the Input Capture Register

(ICRn) is set by the WGMn[3:0] to be used as the TOP value, the ICFn Flag is set when the

counter reaches the TOP value.

ICFn is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,

ICFn can be cleared by writing a logic one to its bit location.

• Bit 3 – OCFnC: Timer/Countern, Output Compare C Match Flag

This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output

Compare Register C (OCRnC).

Note that a Forced Output Compare (FOCnC) strobe will not set the OCFnC Flag.

OCFnC is automatically cleared when the Output Compare Match C Interrupt Vector is exe-

cuted. Alternatively, OCFnC can be cleared by writing a logic one to its bit location.

Bit

76543210

0x16 (0x36)

–

–ICF1

–

OCF1C

OCF1B

OCF1A

TOV1

TIFR1

Read/Write

R/W

Initial Value

00000000

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