ATtiny167 datasheet(135/282 Pages) ATMEL

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7728D–AVR–07/09

ATtiny87/ATtiny167

12.11.2

Timer/Counter1 Control Register B – TCCR1B

• Bit 7 – ICNC1: Input Capture Noise Canceler

Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler

is activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires

four successive equal valued samples of the ICP1 pin for changing its output. The Input Cap-

ture is therefore delayed by four Oscillator cycles when the noise canceler is enabled.

• Bit 6 – ICES1: Input Capture Edge Select

This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture

event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and

when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture.

When a capture is triggered according to the ICES1 setting, the counter value is copied into

the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and

this can be used to cause an Input Capture Interrupt, if this interrupt is enabled.

When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the

TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input

Capture function is disabled.

• Bit 5 – Reserved Bit

This bit is reserved for future use. For ensuring compatibility with future devices, this bit must

be written to zero when TCCR1B is written.

• Bit 4:3 – WGM13:2: Waveform Generation Mode

See TCCR1A Register description.

• Bit 2:0 – CS12:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter, see Fig-

ure 12-11 and Figure 12-12.

Bit

765

210

ICNC1

ICES1

–

WGM13

WGM12

CS12

CS11

CS10

TCCR1B

Read/Write

R/W

Initial Value

Table 12-5.

Clock Select Bit Description

CS12

CS11

CS10

Description

No clock source (Timer/Counter stopped).

001

clkI/O/1 (No prescaling)

010

clkI/O/8 (From prescaler)

011

clkI/O/64 (From prescaler)

100

clkI/O/256 (From prescaler)

101

clkI/O/1024 (From prescaler)

External clock source on T1 pin. Clock on falling edge.

External clock source on T1 pin. Clock on rising edge.

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