ATtiny167 datasheet(88/282 Pages) ATMEL

88 / 282 page

7728D–AVR–07/09

ATtiny87/ATtiny167

Figure 10-1. 8-bit Timer/Counter0 Block Diagram

The Timer/Counter (TCNT0) and Output Compare Register (OCR0A) are 8-bit registers. Inter-

rupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register

(TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Register

(TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked

from the XTAL1/2 pins, as detailed later in this section. The asynchronous operation is con-

trolled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls

which clock source the Timer/Counter uses to increment (or decrement) its value. The

Timer/Counter is inactive when no clock source is selected. The output from the Clock Select

logic is referred to as the timer clock (clk

T0).

The double buffered Output Compare Register (OCR0A) is compared with the Timer/Counter

value at all times. The result of the compare can be used by the Waveform Generator to gen-

erate a PWM or variable frequency output on the Output Compare pin (OC0A). See ”Output

Compare Unit” on page 90. for details. The compare match event will also set the compare

flag (OCF0A) which can be used to generate an Output Compare interrupt request.

Timer/Counter

TCNTn

Waveform

Generation

OCnx

= 0

Control Logic

= 0xFF

TOP

BOTTOM

count

clear

direction

TOVn

(Int.Req.)

OCnx

(Int.Req.)

Synchronization Unit

OCRnx

TCCRnx

ASSRn

Status flags

clk

I/O

clk

ASY

Synchronized Status flags

asynchronous mode

select (ASn)

XTAL2

Oscillator

XTAL1

Prescaler

clk

I/O

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