MX844

7

08/25/06

Drawing No. 084423

www.claremicronix.com

IXYS

MX844

Example internal divider settings and clock frequencies for standard baud rates:

CR7:5

M1

Baud

ADC

Clock

baud

ADC

Clock

baud

ADC

divider

divider

(MHz)

rate

conv/s

(MHz)

rate

conv/s

000

1

8*52

8

12.0

28.8K

366

16.0

38.4K

488

001

1

4*52

4

6.0

28.8K

366

8.0

38.4K

488

010

1

12*64

12

11.059

14.4K

225

14.746

19.2K

300

011

1

13*64

13

12.0

14.4K

225

16.0

19.2K

300

000

0

8*64

8

14.746

28.8K

450

9.83

19.2K

300

001

0

4*64

4

14.746

57.6K

900

9.83

38.4K

600

010

0

6*64

6

11.059

28.8K

450

14.746

38.4K

600

011

0

3*64

3

11.059

57.6K

900

7.37

38.4K

600

100

1

8*128

8*4*5

9.83

9600

15

101

1

9*128

9*4*5

11.059

9600

15

110

1

12*128

12*4*5 14.746

9600

15

111

1

13*128

13*4*5 16.0

9600

15

100

0

8*128

8*4*6

9.83

9600

12.5

101

0

9*128

9*4*6

11.059

9600

12.5

110

0

12*128

12*4*6 14.746

9600

12.5

111

0

13*128

13*4*6 16.0

9600

12.5

SYNCHRONOUS SERIAL I/O

The MX844 (slave) can communicate with a microcomputer (master) via a three wire plus chip select

serial interface. The control register, the two digital comparator values, and the ADC result are accessed

by specifying a 3-bit address A[2:0]. Chip select CS, serial clock SCK, and serial data input SDI are

output from the master controller to the MX844. Serial data output SDO is driven by the MX844 when

SERIAL INTERFACE TIMING

tClock = the period of the X1 input clock

READ:

1.5 * tClock min

CS

SCK

SDI

RW = 0

A2

A1

A0

1.2 * tClock min

SDO

B7

B6

B5

B4

B3

B2

B1

B0

WRITE:

2 * tClock max

SDI

RW = 1

A2

A1

A0

B7

B6

B5

B4

B3 B2

B1

B0

SCK minimum high or low time is 3 * tClock.

SDO is high impedance until data read out, and then returns to high impedance due to the rising edge of CS.