2

6483A–ATARM–04-Aug-09

ATSAM3U Errata

1.2

Errata

1.2.1

Flash Memory

1.2.1.1

Higher power consumption than expected can be seen when reading Flash in 64-bit mode.

Workaround

Use 128-bit mode instead.

Problem Fix

This issue will be fixed in the next revision.

1.2.1.2

FLASH: Flash issue running at frequency lower than 2.5 MHz

When the system clock (MCK) is lower then 2.5 MHz with 1 or 2 Wait State (WS) programmed in

the EEFC_FMR, the Cortex fetches wrong instructions.

Workaround

Do not use 1 or 2 WS when running at a frequency lower than 2.5 MHz.

Problem Fix

This issue will be fixed in the next revision.

1.2.2

12-bit ADC (ADC12B)

1.2.2.1

ADC12B: Single Ended Mode

When enabling a channel in single ended mode, AD12B0 (CH0) for example, the associated

channel in differential mode, AD12B1 and its associated pin are also activated. If the application

is using the PIO pin multiplexed with AD12B1 input, the PIO pin will switch to input Analog Mode

when the channel is enabled. However, the conversion result on AD12B0 channel is not

impacted.

Workaround

None.

Problem Fix

This issue will be fixed in the next revision.

1.2.2.2

ADC12B: Differential Mode

When enabling a channel in differential mode, CH0 (AD12B0-AD12B1 inputs) for example, only

the AD12B0 input will be set to input analog mode automatically by the ADC Controller.

Workaround

The associated differential input channel, AD12B1 must be enabled by the user’s software, i.e.,

CH1.

Problem Fix

This issue will be fixed in the next revision.

1.2.2.3

ADC12B: Wrong Mode after reset

After reset the ADC is not in Off Mode, but in Standby Mode leading to current consumption on

VDDANA (1.4 mA. instead of 0.1 µA).

Workaround