6

ICS95V857

0674U—01/27/09

Notes:

1.

Refers to transition on noninverting output in PLL bypass mode.

2.

While the pulse skew is almost constant over frequency, the duty cycle error

3.

Switching characteristics guaranteed for application frequency range.

4.

Static phase offset shifted by design.

Timing Requirements

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

Max clock frequency

2.5V+0.2V @ 25

45

233

MHz

Application Frequency

Range

2.5V+0.2V @ 25

95

220

MHz

Input clock duty cycle

40

60

%

CLK stabilization

15

µs

Switching Characteristics (see note 3)

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS

Low-to high level

propagation delay time

1

CLK_IN to any output

3.5

ns

High-to low level propagation

delay time

1

CLK_IN to any output

3.5

ns

Output enable time

PD# to any output

3

ns

Output disable time

tdis

PD# to any output

3

ns

Period jitter

100MHz to 200MHz

-30

30

ps

Half-period jitter

t(jit_hper)

100MHz to 200MHz

-75

75

ps

Input clock slew rate

14

V/ns

Output clock slew rate

12

V/ns

Cycle to Cycle Jitter

1

100MHz to 200MHz

-50

50

ps

Static Phase Offset

4

-50

0

50

ps

Output to Output Skew

40

ps