AT89LP213 datasheet(25/98 Pages) ATMEL

25 / 98 page

3538D–MICRO–10/09

AT89LP213/214

Figure 13-1. Quasi-bidirectional Output

13.1.2

Input-only Mode

The input only port configuration is shown in Figure 13-2. The output drivers are tristated. The

input includes a Schmitt-triggered input for improved input noise rejection. The input circuitry of

P1.3, P3.2 and P3.3 is not disabled during Power-down (see Figure 13-3). Input pins can be

safely driven to 5.5V even when operating at lower V

CC levels; however, the input threshold of

the Schmitt trigger will be set by the V

CC level and must be taken into consideration.

Figure 13-2. Input Only

Figure 13-3. Input Only for P1.3, P3.2 and P3.3

13.1.3

Open-drain Output

The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor

of the port pin when the port latch contains a logic “0”. To be used as a logic output, a port con-

figured in this manner must have an external pull-up, typically a resistor tied to V

CC. The pull-

down for this mode is the same as for the quasi-bidirectional mode. The open-drain port configu-

ration is shown in Figure 13-4.The input circuitry of P1.3, P3.2 and P3.3 is not disabled during

Power-down (see Figure 13-3). Open-drain pins can be safely pulled high to 5.5V even when

operating at lower V

CC levels; however, the input threshold of the Schmitt trigger will be set by

the V

CC level and must be taken into consideration.

1 Clock Delay

(D Flip-Flop)

Strong

Very

Weak

Port

VCC

From Port

Input

Data

PWD

Port

Input

Data

PWD

Port

Input

Data

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