ATmega128 datasheet(235/386 Pages) ATMEL

235 / 386 page

235

2467S–AVR–07/09

ATmega128

Differential Gain

Channels

When using differential gain channels, certain aspects of the conversion need to be taken into

consideration.

Differential conversions are synchronized to the internal clock CK

ADC2 equal to half the ADC

clock. This synchronization is done automatically by the ADC interface in such a way that the

sample-and-hold occurs at a specific edge of CK

ADC2. A conversion initiated by the user (i.e., all

single conversions, and the first free running conversion) when CK

ADC2 is low will take the same

amount of time as a single ended conversion (13 ADC clock cycles from the next prescaled

clock cycle). A conversion initiated by the user when CK

ADC2 is high will take 14 ADC clock

cycles due to the synchronization mechanism. In free running mode, a new conversion is initi-

ated immediately after the previous conversion completes, and since CK

ADC2 is high at this time,

all automatically started (i.e., all but the first) free running conversions will take 14 ADC clock

cycles.

The gain stage is optimized for a bandwidth of 4 kHz at all gain settings. Higher frequencies may

be subjected to non-linear amplification. An external low-pass filter should be used if the input

signal contains higher frequency components than the gain stage bandwidth. Note that the ADC

clock frequency is independent of the gain stage bandwidth limitation. E.g. the ADC clock period

may be 6 µs, allowing a channel to be sampled at 12 kSPS, regardless of the bandwidth of this

channel.

Changing Channel

or Reference

Selection

The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary

selection only takes place at a safe point during the conversion. The channel and reference

selection is continuously updated until a conversion is started. Once the conversion starts, the

channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Con-

tinuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in

ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after

ADSC is written. The user is thus advised not to write new channel or reference selection values

to ADMUX until one ADC clock cycle after ADSC is written.

Special care should be taken when changing differential channels. Once a differential channel

has been selected, the gain stage may take as much as 125 µs to stabilize to the new value.

Thus conversions should not be started within the first 125 µs after selecting a new differential

channel. Alternatively, conversion results obtained within this period should be discarded.

The same settling time should be observed for the first differential conversion after changing

ADC reference (by changing the REFS1:0 bits in ADMUX).

If the JTAG Interface is enabled, the function of ADC channels on PORTF7:4 is overridden.

Refer to Table 42, “Port F Pins Alternate Functions,” on page 83.

Table 95. ADC Conversion Time

Condition

Sample & Hold (Cycles from

Start of Conversion)

Conversion Time

(Cycles)

First conversion

13.5

Normal conversions, single ended

1.5

Normal conversions, differential

1.5/2.5

13/14

ATmega128 датащи(PDF) 235 Page - ATMEL Corporation

ATmega128 датащи(HTML) 235 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL