ATmega128 datasheet(225/386 Pages) ATMEL

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2467S–AVR–07/09

ATmega128

Status $F8 indicates that no relevant information is available because the TWINT flag is not set.

This occurs between other states, and when the TWI is not involved in a serial transfer.

Status $00 indicates that a bus error has occurred during a Two-wire Serial Bus transfer. A bus

error occurs when a START or STOP condition occurs at an illegal position in the format frame.

Examples of such illegal positions are during the serial transfer of an address byte, a data byte,

or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the

TWSTO flag must set and TWINT must be cleared by writing a logic one to it. This causes the

TWI to enter the not addressed slave mode and to clear the TWSTO flag (no other bits in TWCR

are affected). The SDA and SCL lines are released, and no STOP condition is transmitted.

Combining Several

TWI Modes

In some cases, several TWI modes must be combined in order to complete the desired action.

Consider for example reading data from a serial EEPROM. Typically, such a transfer involves

the following steps:

The transfer must be initiated

The EEPROM must be instructed what location should be read

The reading must be performed

The transfer must be finished

Note that data is transmitted both from master to slave and vice versa. The master must instruct

the slave what location it wants to read, requiring the use of the MT mode. Subsequently, data

must be read from the slave, implying the use of the MR mode. Thus, the transfer direction must

be changed. The master must keep control of the bus during all these steps, and the steps

should be carried out as an atomical operation. If this principle is violated in a multimaster sys-

tem, another master can alter the data pointer in the EEPROM between steps 2 and 3, and the

master will read the wrong data location. Such a change in transfer direction is accomplished by

transmitting a REPEATED START between the transmission of the address byte and reception

of the data. After a REPEATED START, the master keeps ownership of the bus. The following

figure shows the flow in this transfer.

Figure 104. Combining Several TWI Modes to Access a Serial EEPROM

Multi-master

Systems and

Arbitration

If multiple masters are connected to the same bus, transmissions may be initiated simultane-

ously by one or more of them. The TWI standard ensures that such situations are handled in

such a way that one of the masters will be allowed to proceed with the transfer, and that no data

Table 92. Miscellaneous States

Status Code

(TWSR)

Prescaler Bits

are 0

Status of the Two-wire Serial

Bus and Two-wire Serial Inter-

face Hardware

Application Software Response

Next Action Taken by TWI Hardware

To/from TWDR

To TWCR

STA

STO

TWINT

TWEA

$F8

No relevant state information

available; TWINT = “0”

No TWDR action

No TWCR action

Wait or proceed current transfer

$00

Bus error due to an illegal

START or STOP condition

No TWDR action

Only the internal hardware is affected, no STOP condi-

tion is sent on the bus. In all cases, the bus is released

and TWSTO is cleared.

Master Transmitter

Master Receiver

S = START

Rs = REPEATED START

P = STOP

Transmitted from master to slave

Transmitted from slave to master

SLA+W

ADDRESS

SLA+R

DATA

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