ATmega128 datasheet(223/386 Pages) ATMEL

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223

2467S–AVR–07/09

ATmega128

The upper seven bits are the address to which the Two-wire Serial Interface will respond when

addressed by a master. If the LSB is set, the TWI will respond to the general call address ($00),

otherwise it will ignore the general call address.

TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable

the acknowledgment of the device’s own slave address or the general call address. TWSTA and

TWSTO must be written to zero.

When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own

slave address (or the general call address if enabled) followed by the data direction bit. If the

direction bit is “1” (read), the TWI will operate in ST mode, otherwise SR mode is entered. After

its own slave address and the write bit have been received, the TWINT flag is set and a valid

status code can be read from TWSR. The status code is used to determine the appropriate soft-

ware action. The appropriate action to be taken for each status code is detailed in Table 91. The

Slave Transmitter mode may also be entered if arbitration is lost while the TWI is in the Master

mode (see state $B0).

If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the trans-

fer. State $C0 or state $C8 will be entered, depending on whether the master receiver transmits

a NACK or ACK after the final byte. The TWI is switched to the not addressed slave mode, and

will ignore the master if it continues the transfer. Thus the master receiver receives all “1” as

serial data. State $C8 is entered if the master demands additional data bytes (by transmitting

ACK), even though the slave has transmitted the last byte (TWEA zero and expecting NACK

from the master).

While TWEA is zero, the TWI does not respond to its own slave address. However, the Two-wire

Serial Bus is still monitored and address recognition may resume at any time by setting TWEA.

This implies that the TWEA bit may be used to temporarily isolate the TWI from the Two-wire

Serial Bus.

In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA

bit is set, the interface can still acknowledge its own slave address or the general call address by

using the Two-wire Serial Bus clock as a clock source. The part will then wake up from sleep

and the TWI will hold the SCL clock will low during the wake up and until the TWINT flag is

cleared (by writing it to one). Further data transmission will be carried out as normal, with the

AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the

SCL line may be held low for a long time, blocking other data transmissions.

Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte

present on the bus when waking up from these sleep modes.

TWAR

TWA6

TWA5

TWA4

TWA3

TWA2

TWA1

TWA0

TWGCE

value

Device’s Own Slave Address

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

100

Table 91. Status Codes for Slave Transmitter Mode

Status Code

(TWSR)

Prescaler Bits

are 0

Status of the Two-wire Serial Bus

and

Two-wire

Serial

Interface

Hardware

Application Software Response

Next Action Taken by TWI Hardware

To/from TWDR

To TWCR

STA

STO

TWINT

TWEA

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