ATmega162 datasheet(124/324 Pages) ATMEL

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2513K–AVR–07/09

ATmega162/V

The PWM resolution for the phase and frequency correct PWM mode can be defined by either

ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and

the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can

be calculated using the following equation:

In phase and frequency correct PWM mode the counter is incremented until the counter value

matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). The

counter has then reached the TOP and changes the count direction. The TCNTn value will be

equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency

correct PWM mode is shown on Figure 54. The figure shows phase and frequency correct PWM

mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram

shown as a histogram for illustrating the dual-slope operation. The diagram includes non-

inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes repre-

sent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a

Compare Match occurs.

Figure 54. Phase and Frequency Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx

Registers are updated with the double buffer value (at BOTTOM). When either OCRnA or ICRn

is used for defining the TOP value, the OCnA or ICFn Flag set when TCNTn has reached TOP.

The Interrupt Flags can then be used to generate an interrupt each time the counter reaches the

TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is higher or

equal to the value of all of the compare registers. If the TOP value is lower than any of the com-

pare registers, a Compare Match will never occur between the TCNTn and the OCRnx.

As Figure 54 shows the output generated is, in contrast to the phase correct mode, symmetrical

in all periods. Since the OCRnx Registers are updated at BOTTOM, the length of the rising and

the falling slopes will always be equal. This gives symmetrical output pulses and is therefore fre-

quency correct.

RPFCPWM

TOP 1

()

log

()

log

-----------------------------------

OCRnx/TOP Update and

TOVn Interrupt Flag Set

(Interrupt on Bottom)

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

TCNTn

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

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