ATmega162 datasheet(121/324 Pages) ATMEL

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2513K–AVR–07/09

ATmega162/V

pare registers, a Compare Match will never occur between the TCNTn and the OCRnx. Note

that when using fixed TOP values the unused bits are masked to zero when any of the OCRnx

Registers are written.

The procedure for updating ICRn differs from updating OCRnA when used for defining the TOP

value. The ICRn Register is not double buffered. This means that if ICRn is changed to a low

value when the counter is running with none or a low prescaler value, there is a risk that the new

ICRn value written is lower than the current value of TCNTn. The result will then be that the

counter will miss the Compare Match at the TOP value. The counter will then have to count to

the MAX value (0xFFFF) and wrap around starting at 0x0000 before the Compare Match can

occur. The OCRnA Register however, is double buffered. This feature allows the OCRnA I/O

location to be written anytime. When the OCRnA I/O location is written the value written will be

put into the OCRnA Buffer Register. The OCRnA Compare Register will then be updated with

the value in the Buffer Register at the next timer clock cycle the TCNTn matches TOP. The

update is done at the same timer clock cycle as the TCNTn is cleared and the TOVn Flag is set.

Using the ICRn Register for defining TOP works well when using fixed TOP values. By using

ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However,

if the base PWM frequency is actively changed (by changing the TOP value), using the OCRnA

as TOP is clearly a better choice due to its double buffer feature.

In fast PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins.

Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output

can be generated by setting the COMnx1:0 to three (See Table on page 129). The actual OCnx

value will only be visible on the port pin if the data direction for the port pin is set as output

(DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at

the Compare Match between OCRnx and TCNTn, and clearing (or setting) the OCnx Register at

the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). For Timer/Counter3 also

prescaler factors 16 and 32 are available.

The extreme values for the OCRnx Register represents special cases when generating a PWM

waveform output in the fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000) the out-

put will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCRnx equal to TOP

will result in a constant high or low output (depending on the polarity of the output set by the

COMnx1:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OCnA to toggle its logical level on each Compare Match (COMnA1:0 = 1). This applies only

if OCRnA is used to define the TOP value (WGMn3:0 = 15). The waveform generated will have

a maximum frequency of f

OCnA = fclk_I/O/2 when OCRnA is set to zero (0x0000). This feature is

similar to the OCnA toggle in CTC mode, except the double buffer feature of the output compare

unit is enabled in the fast PWM mode.

fOCnxPWM

clk_I/O

TOP

()

⋅

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