ATmega16 datasheet(232/357 Pages) ATMEL

232 / 357 page

232

2466S–AVR–05/09

ATmega16(L)

Boundary-scan

Chain

The Boundary-scan chain has the capability of driving and observing the logic levels on the digi-

tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having

Off-chip connection.

Scanning the Digital

Port Pins

Figure 116 shows the Boundary-scan Cell for a bi-directional port pin with pull-up function. The

cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn – function, and a

bi-directional pin cell that combines the three signals Output Control – OCxn, Output Data –

ODxn, and Input Data – IDxn, into only a two-stage Shift Register. The port and pin indexes are

not used in the following description.

The Boundary-scan logic is not included in the figures in the datasheet. Figure 117 shows a sim-

ple digital Port Pin as described in the section “I/O Ports” on page 50. The Boundary-scan

details from Figure 116 replaces the dashed box in Figure 117.

When no alternate port function is present, the Input Data – ID – corresponds to the PINxn Reg-

ister value (but ID has no synchronizer), Output Data corresponds to the PORT Register, Output

Control corresponds to the Data Direction – DD Register, and the Pull-up Enable – PUExn – cor-

responds to logic expression PUD · DDxn · PORTxn.

Digital alternate port functions are connected outside the dotted box in Figure 117 to make the

scan chain read the actual pin value. For Analog function, there is a direct connection from the

external pin to the analog circuit, and a scan chain is inserted on the interface between the digi-

tal logic and the analog circuitry.

Figure 116. Boundary-scan Cell for Bidirectional Port Pin with Pull-up Function.

Port Pin (PXn)

Vcc

EXTEST

To Next Cell

ShiftDR

Output Control (OC)

Pullup Enable (PUE)

Output Data (OD)

Input Data (ID)

From Last Cell

UpdateDR

ClockDR

FF2

LD2

FF1

LD1

LD0

FF0

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