ATmega16 datasheet(146/357 Pages) ATMEL

146 / 357 page

146

2466S–AVR–05/09

ATmega16(L)

Figure 70. Clock Generation Logic, Block Diagram

Signal description:

txclk

Transmitter clock (Internal Signal).

rxclk

Receiver base clock (Internal Signal).

xcki

Input from XCK pin (Internal Signal). Used for synchronous Slave operation.

xcko

Clock output to XCK pin (Internal Signal). Used for synchronous Master

operation.

fosc

XTAL pin frequency (System Clock).

Internal Clock

Generation – The

Baud Rate Generator

Internal clock generation is used for the asynchronous and the synchronous Master modes of

operation. The description in this section refers to Figure 70.

The USART Baud Rate Register (UBRR) and the down-counter connected to it function as a

programmable prescaler or baud rate generator. The down-counter, running at system clock

(fosc), is loaded with the UBRR value each time the counter has counted down to zero or when

the UBRRL Register is written. A clock is generated each time the counter reaches zero. This

clock is the baud rate generator clock output (= fosc/(UBRR+1)). The Transmitter divides the

baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator out-

put is used directly by the receiver’s clock and data recovery units. However, the recovery units

use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the

UMSEL, U2X and DDR_XCK bits.

Table 60 contains equations for calculating the baud rate (in bits per second) and for calculating

the UBRR value for each mode of operation using an internally generated clock source.

Prescaling

Down-Counter

/ 2

UBRR

/ 4

/ 2

fosc

UBRR+1

Sync

OSC

XCK

txclk

U2X

UMSEL

DDR_XCK

xcki

xcko

DDR_XCK

rxclk

Edge

Detector

UCPOL

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