AT88SC25616C

5

5017KJS–SMEM–08/09

Table 3.

AC Characteristics

(unless otherwise noted)

Symbol

Parameter

Min

Max

Units

1

5

MHZ

1

4

MHZ

Synch Clock Frequency

0

1

MHZ

Clock Duty cycle

40

60

%

Rise Time - I/O, RST

1

μS

Fall Time - I/O, RST

1

μS

Rise Time - CLK

9% x period

μS

Fall Time - CLK

9% x period

μS

Clock Low to Data Out Valid

35

nS

Start Hold Time

200

nS

Start Set-up Time

200

nS

Data In Hold Time

10

nS

Data In Set-up Time

100

nS

Stop Set-up Time

200

nS

Data Out Hold Time

20

nS

Write Cycle Time (at 25°C)

5

mS

Write Cycle Time (-40° to +85°C)

7

mS

4.

Device Operation for Synchronous Protocols

CLOCK and DATA TRANSITIONS

: The SDA pin is normally pulled high with an external device. Data on the SDA pin

may change only during SCL low time periods (see Figure 5 on page 7). Data changes

during SCL high periods will indicate a start or stop condition as defined below.

START CONDITION

:

A high-to-low transition of SDA with SCL high is a start condition which must precede any

other command (see Figure 6 on page 7).

STOP CONDITION

:

A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the

stop command will place the EEPROM in a standby power mode (see Figure 6 on page 7).

ACKNOWLEDGE

:

All addresses and data words are serially transmitted to and from the EEPROM in 8-bit

words. The EEPROM sends a zero to acknowledge that it has received each word. This

happens during the ninth clock cycle.

MEMORY RESET

:

After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by

following these steps:

1.

Clock up to 9 cycles.

2.

Look for SDA high in each cycle while SCL is high.

3.

Create a start condition.