TLE7263E datasheet(21/63 Pages) INFINEON

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TLE 7263E

Features

Data Sheet

Rev. 1.51, 2007-06-22

4.11

SPI (Serial Peripheral Interface)

The 16-bit wide Programming or Input Word (see Table 3) is read in via the data input

DI, which is synchronized with the clock input CLK supplied by the

µC. The Diagnosis or

Output Word appears synchronously at the data output DO (see Figure 10).

The transmission cycle begins when the chip is selected by the Chip Select Not input

CSN (“low” active). After the CSN input returns from L to H, the word that has been read

in becomes the new control word. The DO output switches to tristate status at this point,

thereby releasing the DO bus for other usage.

The state of DI is shifted into the input register with every falling edge on CLK. The state

of DO is shifted out of the output register after every rising edge on CLK. The number of

received input clocks is supervised by a modulo-16 operation and the Input / Control

Word is discarded in case of a mismatch. This error is flagged by the WKO set to “low”

and in the following SPI output by a “high” at the data output (DO pin) before the first

rising edge of the clock is received.

Figure 11

16-Bit SPI Input Data / Control Word

15 14 13 12 11 10

Mode Selection

Bits

Configuration

Select

Configuration Registers

OUTHS

On/Off

Input

Data

Active

LIN Sleep

Sleep

Reserved

000

001

010

011

100

101

Reset

Thres.

Reset

Delay

Window Watchdog Timing

Bit Position: 10 .. 5

MON2

On/Off

MON3

On/Off

MON4

On/Off

110

111

LIN

10.4k

MON1

On/Off

Res.

Reserved

(Watchdog Trigger Register)

On/Off

CC2

On/off

Cyclic Sense / Wake Timing

Bit Position: 9 .. 5

SPI_Bit_Settings

not valid

LIN RxD Only

Stop

LSB

MSB

MS0

MS1

MS2

CS0

CS1

CTM

On/Off

Select

OUTHS

„off“

OUTHS

On-Time

Cyclic

Sense /

Wake

Active

CAN Sleep

CAN RxD Only

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