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USB4640 датащи(PDF) 24 Page - SMSC Corporation

номер детали USB4640
подробное описание детали  High Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller
PDF  64 Pages
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производитель  SMSC [SMSC Corporation]
домашняя страница  http://www.smsc.com
Logo SMSC - SMSC Corporation

USB4640 датащи(HTML) 24 Page - SMSC Corporation

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High Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller
Datasheet
Revision 1.0 (06-09-09)
24
SMSC USB4640/USB4640i
DATASHEET
6.4
ROM BOOT Sequence
After power-on reset, the internal firmware checks for an external SPI flash device that contains a valid
signature of "2DFU" (device firmware upgrade) beginning at address 0xFFFA. If a valid signature is
found, then the external ROM is enabled and code execution begins at address 0x0000 in the external
SPI device. Otherwise, code execution continues from the internal ROM.
If there is no SPI ROM detected, the internal firmware then checks for the presence of an I2C ROM.
The firmware looks for the signature ‘ATA2’ at the offset of FCh-FFh and ‘ecf1’ at the offset of 17Ch-
17Fh in the I2C ROM. The firmware reads in the I2C ROM to configure the hardware and software
internally. Please refer to Section 8.3.2, "EEPROM Data Descriptor," on page 29 for the details of the
configuration options.
The SPI ROM required for the USB4640/USB4640i is a recommended minimum of 1 Mbit and support
either 30 MHz or 60 MHz. The frequency used is set using the SPI_SPD_SEL. For 30 MHz operation,
this pin must be pulled to ground through a 100 k
Ω resistor. For 60 MHz operation, this pin must pulled
up through a 100 k
Ω resistor.
The SPI_SPD_SEL pin is used to choose the speed of the SPI interface. During nRESET assertion,
this pin will be tri-stated with the weak pull-down resistor enabled. When nRESET is negated, the value
on the pin will be internally latched, and the pin will revert to SPI_DO functionality. The internal pull-
down will be disabled.
The firmware can determine the speed of operation on the SPI port by checking the SPI_SPEED in
the SPI_CTL register (0x2400 - RESET = 0x02). Both 1- and 2-bit SPI operation is supported. For
optimum throughput, a 2-bit SPI ROM is recommended. Both mode 0 and mode 3 SPI ROMS are also
supported.
Figure 6.4 SPI ROM Connection
Figure 6.5 I2C Connection
SPI ROM
SPI_CE_n
SPI_CLK / GPIO4 / SCL
SPI_DI
SPI_DO / GPIO5 / SDA / SPI_SPD_SEL
CE#
CLK
SI
SO
USB4640/40i
I2C ROM
SCL
SDA
3. 3 V
3. 3 V
10 K
10 K
USB4640/40i



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