LTC2605IGNPBF datasheet(13/18 Pages) LINER

13 / 18 page

LTC2605/LTC2615/LTC2625

2605fa

OPERATION

The format of the three data bytes is shown in Figure 2.

The ﬁrst byte of the input word consists of the 4-bit com-

mand and 4-bit DAC address. The next two bytes consist

of the 16-bit data word. The 16-bit data word consists of

the 16-, 14- or 12-bit input code, MSB to LSB, followed by

0, 2 or 4 don’t care bits (LTC2605, LTC2615 and LTC2625

respectively). A typical I2C write transaction is shown in

Figure 3.

The command (C3-C0) and address (A3-A0) assignments

are shown in Table 1. The ﬁrst four commands in the table

consist of write and update operations. A write operation

loads the 16-bit data word from the 32-bit shift register

into the input register of the selected DAC, n. An update

operation copies the data word from the input register to

the DAC register. Once copied into the DAC register, the

data word becomes the active 16-, 14- or 12-bit input

code, and is converted to an analog voltage at the DAC

output. The update operation also powers up the selected

DAC if it had been in power-down mode. The data path

and registers are shown in the Block Diagram.

Power-Down Mode

For power-constrained applications, power-down mode

can be used to reduce the supply current whenever less

than eight outputs are needed. When in power down, the

buffer ampliﬁers and reference inputs are disabled and

draw essentially zero current. The DAC outputs are put into

a high impedance state, and the output pins are passively

pulled to ground through individual 90k resistors. When

all eight DACs are powered down, the bias generation

circuit is also disabled. Input and DAC registers are not

disturbed during power down.

Any channel or combination of channels can be put into

power-down mode by using command 0100b in combi-

nation with the appropriate DAC address, (n). The 16-bit

data word is ignored. The supply and reference currents

are reduced by approximately 1/8 for each DAC powered

down; the effective resistance at REF (Pin 6) rises accord-

ingly, becoming a high impedance input (typically >1GΩ)

when all eight DACs are powered down.

Normal operation can be resumed by executing any com-

mand which includes a DAC update, as shown in Table 1.

The selected DAC is powered up as its voltage output is

updated.

There is an initial delay as the DAC powers up before it

begins its usual settling behavior. If less than eight DACs

are in a powered-down state prior to the updated com-

mand, the power-up delay is 5μs. If, on the other hand,

all eight DACs are powered down, then the bias genera-

tion circuit is also disabled and must be restarted. In this

case, the power-up delay is greater: 12μs for VCC = 5V,

30μs for VCC = 3V.

INPUT WORD

WRITE WORD PROTOCOL FOR LTC2605/LTC2615/LTC2625

INPUT WORD (LTC2605)

SLAVE ADDRESS

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

2605 F02

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

D13

D14

D15

D12 D11 D10 D9

D7 D6

D1 D0

INPUT WORD (LTC2615)

D11

D12

D13

D10 D9

D5 D4

INPUT WORD (LTC2625)

D10

D11

D3 D2

Figure 2

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