MPC8377ECVRAGDA datasheet(25/124 Pages) FREESCALE

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MPC8377E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC)

8.2.1.2

MII Receive AC Timing Specifications

Table 26 provides the MII receive AC timing specifications.

Figure 8 provides the AC test load for eTSEC.

Figure 8. eTSEC AC Test Load

Table 26. MII Receive AC Timing Specifications

At recommended operating conditions with LVDD of 3.3 V ± 5%.

Parameter

Symbol 1

The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive

timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going

to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals

(D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the

clock reference symbol representation is based on three letters representing the clock of a particular functional. For example,

the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the

appropriate letter: R (rise) or F (fall).

Min

Typical

Max

Unit

Input low voltage

VIL

——

0.7

Input high voltage

VIH

1.9

—

RX_CLK clock period 10 Mbps

tMRX

—

400

—

RX_CLK clock period 100 Mbps

tMRX

—40

—

RX_CLK duty cycle

tMRXH/tMRX

—

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK

tMRDVKH

10.0

—

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK

tMRDXKH

10.0

—

RX_CLK clock rise (20%-80%)

tMRXR

1.0

—

4.0

RX_CLK clock fall time (80%-20%)

tMRXF

1.0

—

4.0

Note:

Output

Z0 = 50 Ω

LVDD/2

RL = 50 Ω

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