MPC5643LF0MLQ8 datasheet(40/98 Pages) FREESCALE

40 / 98 page

MPC5643L Microcontroller Data Sheet, Rev. 3

Preliminary—Subject to Change Without Notice

Package pinouts and signal descriptions

Freescale Semiconductor

VDD_LV_COR

Decoupling pins for core logic and Regulator feedback. Decoupling capacitor

must be connected between this pins and VSS_LV_REGCOR.

VDD_LV1

VSS_LV_COR

VSS_LV_REGCOR0

Decoupling pins for core logic and Regulator feedback. Decoupling capacitor

must be connected between this pins and VDD_LV_REGCOR.

VSS_LV2

VDD_LV_COR

Decoupling pins for core logic. Decoupling capacitor must be connected between

these pins and the nearest VSS_LV_COR pin.

VDD_LV1

VSS_LV_COR

/ 1.2 V Decoupling pins for core logic. Decoupling capacitor must be connected

between these pins and the nearest VDD_LV_COR pin.

VSS_LV2

VDD 1V2

VDD_LV_COR

Decoupling pins for core logic. Decoupling capacitor must be connected between

these pins and the nearest VDD_LV_COR pin.

131

VDD_LV1

VSS 1V2

VSS_LV_COR

Decoupling pins for core logic. Decoupling capacitor must be connected between

these pins and the nearest VDD_LV_COR pin.

132

VSS_LV2

VDD 1V2

VDD_LV_COR /

Decoupling pins for core logic. Decoupling capacitor must be connected between

these pins and the nearest VDD_LV_COR pin.

135

VDD_LV1

VSS 1V2

VSS_LV_COR /

Decoupling pins for core logic. Decoupling capacitor must be connected between

these pins and the nearest VDD_LV_COR pin.

137

VSS_LV2

NOTES:

1 VDD_LV balls are tied together on the 257 MAPBGA substrate.

2 VSS_LV balls are tied together on the 257 MAPBGA substrate.

3 VDD_HV balls are tied together on the 257 MAPBGA substrate.

4 VSS_HV balls are tied together on the 257 MAPBGA substrate.

5 V

PP_TEST must always be tied to ground (VSS) for normal operations.

Table 5. Supply pins (continued)

Supply

Package

Symbol

Description

144

LQFP

257

MAPBGA

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