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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8377ECVRALGA датащи(PDF) 86 Page - Freescale Semiconductor, Inc |
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MPC8377ECVRALGA датащи(HTML) 86 Page - Freescale Semiconductor, Inc |
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86 / 124 page  MPC8377E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2 86 Freescale Semiconductor Package and Pin Listings 21.3 SerDes Transmitter and Receiver Reference Circuits Figure 62 shows the reference circuits for SerDes data lane’s transmitter and receiver. Figure 62. SerDes Transmitter and Receiver Reference Circuits The DC and AC specification of SerDes data lanes are defined in each interface protocol section below in this document based on the application usage: • Section 8, “Ethernet: Enhanced Three-Speed Ethernet (eTSEC)” • Section 15, “PCI Express” • Section 16, “Serial ATA (SATA)” Note that an external AC coupling capacitor is required for the above three serial transmission protocols with the capacitor value defined in specification of each protocol section. 22 Package and Pin Listings This section details package parameters, pin assignments, and dimensions. 22.1 Package Parameters for the MPC8377E TePBGA II The package parameters are provided in the following list. The package type is 31 mm × 31 mm, 689 plastic ball grid array (TePBGA II). Package outline 31 mm × 31 mm Interconnects 689 Pitch 1.00 mm Module height (typical) 2.0 mm to 2.46 mm (maximum) Solder Balls 3.5% Ag, 96.5% Sn Ball diameter (typical) 0.60 mm 50 Ω 50 Ω Receiver Transmitter SD1_TX n or SD2_TX n SD1_TX n or SD2_TX n SD1_RX n or SD2_RX n SD1_RX n or SD2_RX n 50 Ω 50 Ω |
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