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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC5668X датащи(PDF) 39 Page - Freescale Semiconductor, Inc |
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MPC5668X датащи(HTML) 39 Page - Freescale Semiconductor, Inc |
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39 / 66 page  Electrical Characteristics MPC5668x Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without Notice Freescale Semiconductor 39 4.11 ADC Electrical Characteristics 4.12 Flash Memory Electrical Characteristics 2 The maximum frequency value is with frequency modulation disabled. If frequency modulation is enabled, the maximuum frequency value should be de-rated by the percentage of modulation enabled so that the maximum frequency is not exceeded. 3 “Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode. 4 This specification applies to the period required for the PLL to re-lock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). From power up with crystal oscillator reference, lock time will be additive with crystal startup time. 5 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C jitter +Cmod. 6 Modulation depth selected must not result in f PLL value greater than the fPLL maximum specified value. 7 Maximum and minimum variations from programmed modulation depth are 2%, 3%, and 4% peak-to-peak. Use only these settings. 8 Depth tolerance is the programmed modulation depth ±0.25% of f SYS. Initial design target pending silicon evaluation. 9 See the Block Guide for VCO frequency synthesis equations. 10 Modulation rates less than 400 kHz will result in exceedingly long FM calibration durations. Modulation rates greater than 1 MHz will result in reduced calibration accuracy. Table 19. ADC Conversion Specifications (Operating) Spec Characteristic Symbol Min Max Unit 1 Analog High Reference Voltage VRH VDDA –0.5 VDDA V 2 Analog Low Reference Voltage VRL 00.5 V 3 Analog Input Voltage AVIN VRL VRH V 4 Sampling Frequency FS —1.53 MHz 5 Maximum ADC Clock Frequency FMAX —60 MHz 6 Sampling Time VDDA =3.0 V–3.6V VDDA >3.6 V–5.5V tS 250 125 —ns 7 Differential Non Linearity DNL –1.0 1.0 LSB 8 Integral Non Linearity INL –1.5 1.5 LSB 9 Offset Error OFS –1.0 1.0 LSB 10 Gain Error GNE –2.0 2.0 LSB 11 Total Unadjusted Error 1 1 TUE assumes no pin activity on pins adjacent to analog channel or output driver activity on corresponding V DDE segment. TUE –2.0 2.0 LSB Table 20. Flash Program and Erase Specifications1 Spec Characteristic Symbol Min Initial Max2 Max3 Unit 1 Double Word (64 bits) Program Time4 tdwprogram —— 500 μs 2 Page (128 bits and 256 bits) Program Time4 tpprogram — 160 500 μs 3 16 KB Block Pre-program and Erase Time t16kpperase — 1000 5000 ms 4 64 KB Block Pre-program and Erase Time t64kpperase — 1800 5000 ms 5 128 KB Block Pre-program and Erase Time t128kpperase — 2600 7500 ms |
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