SE95_7

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 07 — 2 September 2009

7 of 27

NXP Semiconductors

SE95

Ultra high accuracy digital temperature sensor and thermal watchdog

7.5 Shutdown mode

The device operation mode is selected by programming bit SHUTDOWN of register Conf.

Setting bit SHUTDOWN to logic 1 will put the device into shutdown mode. Resetting bit

SHUTDOWN to logic 0 will return the device to normal mode.

In shutdown mode, the device draws a small current of approximately 7.5

µA and the

interface remains active and register write/read operation can be performed. If the OS

output is in comparator mode, then it remains unchanged. In interrupt mode, the OS

output is reset.

7.6 Power-up default and power-on reset

The SE95 always powers-up in its default state with:

When the power supply voltage is dropped below the device power-on reset level of

approximately 1.9 V (POR) and then rises up again, the device will be reset to its default

condition as listed above.

8.

device under the control of a controller or master device, using two device terminals, SCL

and SDA. The controller must provide the SCL clock signal and write/read data to and

approximately 10 k

Ω, is needed for each of these two terminals. The bus communication

protocols are described in Section 8.7 “Protocols for writing and reading the registers”.

8.1 Slave address

device address pins A2, A1 and A0. Each pin is typically connected either to GND for

address. The other four MSB bits of the address data are preset to 1001 by hard wiring

inside the SE95. Table 4 shows the device's complete address and indicates that up to

8 devices can be connected to the same bus without address conflict. Because the input

pins SCL, SDA and A2 to A0, are not internally biased, it is important that they should not

be left floating in any application.

0Ch is a reserved address for SMBus Alert Response Address (ARA). This is an optional

command from the SMBus specification to allow SMBus devices to respond to an SMBus

master with their slave device if they are generating an interrupt. The SE95 will send a