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PCF8576DH/2 датащи(PDF) 24 Page - NXP Semiconductors |
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PCF8576DH/2 датащи(HTML) 24 Page - NXP Semiconductors |
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24 / 52 page ![]() PCF8576D_9 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 — 25 August 2009 24 of 52 NXP Semiconductors PCF8576D Universal LCD driver for low multiplex rates The I2C-bus protocol is shown in Figure 17. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of two possible PCF8576D slave addresses available. All PCF8576Ds whose SA0 inputs correspond to bit 0 of the slave address respond by asserting an acknowledge in parallel. This I2C-bus transfer is ignored by all PCF8576Ds whose SA0 inputs are set to the alternative level. After an acknowledgement, one or more command bytes follow, that define the status of each addressed PCF8576D. The last command byte sent is identified by resetting its most significant bit, continuation bit C, (see Figure 18). The command bytes are also acknowledged by all addressed PCF8576D on the bus. After the last command byte, one or more display data bytes may follow. Display data bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated and the data directed to the intended PCF8576D device. An acknowledgement after each byte is asserted only by the PCF8576Ds that are addressed via address lines A0, A1 and A2. After the last display byte, the I2C-bus master asserts a STOP condition (P). Alternately a START may be asserted to restart an I2C-bus access. Fig 17. I2C-bus protocol Fig 18. Format of command byte mdb078 S A 0 S 011100 0 A C COMMAND A P A DISPLAY DATA slave address R/W acknowledge by all addressed PCF8576Ds acknowledge by A0, A1 and A2 selected PCF8576D only 1 byte update data pointers and if necessary, subaddress counter n ≥ 1 byte(s) n ≥ 0 byte(s) msa833 REST OF OPCODE C MSB LSB |
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