MFRC522 datasheet(42/96 Pages) NXP

42 / 96 page

MFRC522_33

Product data sheet

PUBLIC

Rev. 3 — 26 October 2009

112133

42 of 96

NXP Semiconductors

MFRC522

Contactless reader IC

9.3.1.10

FIFODataReg register

Input and output of 64 byte FIFO buffer.

9.3.1.11

FIFOLevelReg register

Indicates the number of bytes stored in the FIFO.

9.3.1.12

WaterLevelReg register

Deﬁnes the level for FIFO under- and overﬂow warning.

Table 39.

FIFODataReg register (address 09h); reset value: xxh bit allocation

Bit

Symbol

FIFOData[7:0]

Access

Table 40.

FIFODataReg register bit descriptions

Bit

Symbol

Description

7 to 0

FIFOData[7:0] data input and output port for the internal 64-byte FIFO buffer

FIFO buffer acts as parallel in/parallel out converter for all serial data

stream inputs and outputs

Table 41.

FIFOLevelReg register (address 0Ah); reset value: 00h bit allocation

Bit

Symbol

FlushBuffer

FIFOLevel[6:0]

Access

Table 42.

FIFOLevelReg register bit descriptions

Bit

Symbol

Value Description

FlushBuffer 1

immediately clears the internal FIFO buffer’s read and write pointer

and ErrorReg register’s BufferOvﬂ bit

reading this bit always returns 0

6 to 0 FIFOLevel

[6:0]

indicates the number of bytes stored in the FIFO buffer

writing to the FIFODataReg register increments and reading

decrements the FIFOLevel value

Table 43.

WaterLevelReg register (address 0Bh); reset value: 08h bit allocation

Bit

Symbol

reserved

WaterLevel[5:0]

Access

R/W

MFRC522 датащи(PDF) 42 Page - NXP Semiconductors

MFRC522 датащи(HTML) 42 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

датащи скачать

ссылки URL