PIC18F4321 datasheet(89/402 Pages) MICROCHIP

89 / 402 page

DS39689F-page 89

PIC18F2221/2321/4221/4321 FAMILY

8.0

DATA EEPROM MEMORY

The data EEPROM is a nonvolatile memory array,

separate from the data RAM and program memory, that

is used for long-term storage of program data. It is not

directly mapped in either the register file or program

memory space but is indirectly addressed through the

Special Function Registers (SFRs). The EEPROM is

readable and writable during normal operation over the

entire VDD range.

Four SFRs are used to read and write to the data

EEPROM as well as the program memory. They are:

• EECON1

• EECON2

• EEDATA

• EEADR

The data EEPROM allows byte read and write. When

interfacing to the data memory block, EEDATA holds

the 8-bit data for read/write and the EEADR register

holds the address of the EEPROM location being

accessed.

The EEPROM data memory is rated for high erase/write

cycle endurance. A byte write automatically erases the

location and writes the new data (erase-before-write).

The write time is controlled by an on-chip timer. It will

vary with voltage and temperature as well as from chip

to chip. Please refer to parameter D122 (Table 27-1 in

Section 27.0 “Electrical Characteristics”) for exact

limits.

8.1

EECON1 and EECON2 Registers

Access to the data EEPROM is controlled by two

registers: EECON1 and EECON2. These are the same

registers which control access to the program memory

and are used in a similar manner for the data

EEPROM.

The EECON1 register (Register 8-1) is the control

bit EEPGD determines if the access will be to program

or data EEPROM memory. When clear, operations will

access the data EEPROM memory. When set, program

memory is accessed.

Control bit CFGS determines if the access will be to the

Configuration registers or to program memory/data

EEPROM memory. When set, subsequent operations

access Configuration registers. When CFGS is clear,

the EEPGD bit selects either program Flash or data

EEPROM memory.

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set in hardware when the WREN bit is set and cleared

when the internal programming timer expires and the

write operation is complete.

The WR control bit initiates write operations. The bit

cannot be cleared, only set, in software; it is cleared in

hardware at the completion of the write operation.

Control bits, RD and WR, start read and erase/write

operations, respectively. These bits are set by firmware

and cleared by hardware at the completion of the

operation.

The RD bit cannot be set when accessing program

memory (EEPGD = 1). Program memory is read using

table read instructions. See Section 7.1 “Table Reads

and Table Writes” regarding table reads.

The EECON2 register is not a physical register. It is

used exclusively in the memory write and erase

sequences. Reading EECON2 will read all ‘0’s.

Note:

During normal operation, the WRERR bit

is read as ‘1’. This can indicate that a write

operation was prematurely terminated by

a Reset, or a write operation was

attempted improperly.

Note:

The EEIF interrupt flag bit (PIR2<4>) is set

when the write is complete. It must be

cleared in software.

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