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PIC18F8722 датащи(PDF) 13 Page - Microchip Technology |
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PIC18F8722 датащи(HTML) 13 Page - Microchip Technology |
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13 / 446 page ![]() © 2008 Microchip Technology Inc. DS39646C-page 11 PIC18F8722 FAMILY FIGURE 1-1: PIC18F6527/6622/6627/6722 (64-PIN) BLOCK DIAGRAM Instruction Decode and Control PORTA Data Latch Data Memory (3.9 Kbytes) Address Latch Data Address<12> 12 Access BSR FSR0 FSR1 FSR2 inc/dec logic Address 4 12 4 PCH PCL PCLATH 8 31-Level Stack Program Counter PRODL PRODH 8 x 8 Multiply 8 BITOP 8 8 ALU<8> Address Latch Program Memory (48/64/96/128 Data Latch 20 8 8 Table Pointer<21> inc/dec logic 21 8 Data Bus<8> Table Latch 8 IR 12 3 PCLATU PCU Note 1: See Table 1-3 for I/O port pin descriptions. 2: RG5 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. EUSART1 Comparators MSSP1 Timer2 Timer1 Timer3 Timer0 HLVD ECCP1 BOR ADC 10-bit W Instruction Bus <16> STKPTR Bank 8 State Machine Control Signals Decode 8 8 Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer OSC1(3) OSC2(3) VDD, Brown-out Reset Internal Oscillator Fail-Safe Clock Monitor Precision Reference Band Gap VSS MCLR(2) Block INTRC Oscillator 8 MHz Oscillator Single-Supply Programming In-Circuit Debugger T1OSI T1OSO EUSART2 ECCP2 ROM Latch ECCP3 MSSP2 CCP4 CCP5 PORTC PORTD PORTE PORTF PORTG RA0:RA7(1) RC0:RC7(1) RD0:RD7(1) RE0:RE7(1) RF0:RF7(1) RG0:RG5(1) PORTB RB0:RB7(1) Timer4 Kbytes) |
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