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MCP14700 датащи(PDF) 13 Page - Microchip Technology

номер детали MCP14700
подробное описание детали  Dual Input Synchronous MOSFET Driver
PDF  26 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP14700 датащи(HTML) 13 Page - Microchip Technology

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© 2009 Microchip Technology Inc.
DS22201A-page 13
MCP14700
5.0
APPLICATION INFORMATION
5.1
Bootstrap Capacitor Select
The selection of the bootstrap capacitor is based upon
the total gate charge of the high-side power MOSFET
and the allowable droop in gate drive voltage while the
high-side power MOSFET is conducting.
EQUATION 5-1:
For example:
QGATE = 30 nC
ΔV
DROOP = 200 mV
CBOOT ≥ 0.15 uF
A low ESR ceramic capacitor is recommend with a
maximum voltage rating that exceeds the maximum
input voltage, VCC, plus the maximum supply voltage,
VSUPPLY. It is also recommended that the capacitance
of CBOOT does not exceed 1.2 uF.
5.2
Decoupling Capacitor
Proper
decoupling
of
the
MCP14700
is
highly
recommended to help ensure reliable operation. This
decoupling capacitor should be placed as close to the
MCP14700 as possible. The large currents required to
quickly charge the capacitive loads are provided by this
capacitor.
A
low
ESR
ceramic
capacitor
is
recommended.
5.3
Power Dissipation
The power dissipated in the MCP14700 consists of the
power loss associated with the quiescent power and
the gate charge power.
The quiescent power loss can be calculated by the
following equation and is typically negligible compared
to the gate drive power loss.
EQUATION 5-2:
The main power loss occurs from the gate charge
power loss. This power loss can be defined in terms of
both the high-side and low-side power MOSFETs.
EQUATION 5-3:
C
BOOT
Q
GATE
V
Δ
DROOP
-----------------------------
Where:
CBOOT = Bootstrap capacitor value
QGATE = Total gate charge of the high-side
MOSFET
ΔV
DROO
=
Allowable gate drive voltage droop
P
Q
I
VCC
V
CC
×
=
Where:
PQ = Quiescent power loss
IVCC = No Load Bias Current
VCC = Bias Voltage
P
GATE
P
HIGHDR
P
LOWDR
+
=
P
HIGHDR
V
CC
Q
HIGH
×
F
SW
×
=
P
LOWDR
V
CC
Q
LOW
×
F
SW
×
=
Where:
PGATE = Total Gate Charge Power Loss
PHIGHDR = High-Side Gate Charge Power Loss
PLOWDR = Low-Side Gate Charge Power Loss
VCC = Bias Supply Voltage
QHIGH = High-Side MOSFET Total Gate
Charge
QLOW = Low-Side MOSFET Total GAte
Charge
FSW = Switching Frequency



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