ST7263BEX datasheet(70/186 Pages) STMICROELECTRONICS

70 / 186 page

On-chip peripherals

ST7263Bxx

70/186

Doc ID 7516 Rev 8

Figure 39.

Pulse Width modulation mode timing with 2 output Compare functions

OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1

On timers with only one output Compare register, a fixed frequency PWM signal can be

generated using the output compare and the counter overflow to define the pulse length.

Pulse width modulation mode

Pulse width modulation (PWM) mode enables the generation of a signal with a frequency

and pulse length determined by the value of the OC1R and OC2R registers.

Pulse Width Modulation mode uses the complete output Compare 1 function plus the OC2R

In PWM mode, double buffering is implemented on the output compare registers. Any new

values written in the OC1R and OC2R registers are taken into account only at the end of the

PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1).

Procedure

To use Pulse Width Modulation mode:

Load the OC2R register with the value corresponding to the period of the signal using

the formula in the opposite column.

Load the OC1R register with the value corresponding to the period of the pulse if

(OLVL1 = 0 and OLVL2 = 1) using the formula in the opposite column.

Select the following in the CR1 register:

–

Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a

successful comparison with the OC1R register.

–

Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a

successful comparison with the OC2R register.

Select the following in the CR2 register:

–

Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.

–

Set the PWM bit.

–

Select the timer clock (CC[1:0]) (see Table 24).

COUNTER 34E2

34E2

FFFC

OLVL2

OLVL1

OCMP1

compare2

compare1

compare2

FFFC FFFD FFFE

2ED0

2ED1 2ED2

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