SMB113A/B/SMB117/A

Preliminary Information

Summit Microelectronics, Inc

2111 2.4 6/24/2008

4

INTERNAL BLOCK DIAGRAM

VDDCAP

DEADTIME

+

–

OA

LEVEL

SHIFTER

+

–

+

–

GLITCH

FILTER

GLITCH

FILTER

CLAMP

DUTY

CYCLE

LIMIT

OVER VOLTAGE

DETECTION

100k

DIGITAL TO

ANALOG

CONVERTER

UNDER VOLTAGE

DETECTION

Channel 0,1,2,3

Synchronous buck

PWM Converter

HSDRV[0,1,2,3]

LSDRV[0,1,2,3]

COMP1_CH[0,1,2,3]

COMP2_CH[0,1,2,3]

VM_CH[0,1,2,3]

VREF

VREF

OSC

Fixed 250/400/

800/1000kHz

MAX LIMIT

LOW LIMIT

+

–

PWREN0

HVSUP[0,1,2,3]

VREF

+

–

LEVEL

SHIFTER

+

–

VBATT

DQ

BANDGAP

VREF

2.5V

REGULATOR

VDD_CAP

GND

UV2

SCL

SDA

UV1

SEQUENCING

AND

MONITORING

LOGIC

ENABLE

Figure 3 –SMB113A/B and SMB117/A internal block diagram. Programmable functional blocks include: level

shifters, digital to analog converter and the VM_CH[0,1,2,3] voltage dividers.