XR16M770 datasheet(9/52 Pages) EXAR

9 / 52 page

XR16M770

REV. 1.0.0

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO

2.3

Device Reset

The RESET input resets the internal registers and the serial interface outputs to their default state (see

Table 18). An active high pulse of longer than 40 ns duration will be required to activate the reset function in

the device. Following a power-on reset or an external reset, the M770 is software compatible with previous

generation of UARTs, XR16L570 and ST16C550.

2.4

Internal Registers

The M770 has a set of 16550 compatible registers for controlling, monitoring and data loading and unloading.

These registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER),

a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status and control

registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM/DLD), and a user accessible

scratchpad register (SPR).

Beyond the general 16C550 features and capabilities, the M770 offers enhanced feature registers (EFR, Xon1/

Xoff 1, Xon2/Xoff 2, DLD, FCTR, EMSR, FC and TRIG) that provide automatic RTS and CTS hardware flow

control, automatic Xon/Xoff software flow control, 9-bit (Multidrop) mode, auto RS-485 half duplex control,

different baud rate for TX and RX and fractional baud rate generator. All the register functions are discussed in

full detail later in “Section 3.0, UART INTERNAL REGISTERS” on page 23.

2.5

INT Ouput

The interrupt outputs change according to the operating mode and enhanced features setup. Table 1 and 2

summarize the operating behavior for the transmitter and receiver. Also see Figure 19 through 22.

TABLE 1: INT PIN OPERATION FOR TRANSMITTER

FCR BIT-0 = 0 (FIFO DISABLED)

FCR BIT-0 = 1 (FIFO ENABLED)

INT Pin

LOW = One byte in THR

HIGH = THR empty

LOW = FIFO above trigger level

HIGH = FIFO below trigger level or FIFO empty

TABLE 2: INT PIN OPERATION FOR RECEIVER

FCR BIT-0 = 0 (FIFO DISABLED)

FCR BIT-0 = 1 (FIFO ENABLED)

INT Pin

HIGH = One byte in RHR

LOW = RHR empty

LOW = FIFO below trigger level

HIGH = FIFO above trigger level or RX Data Timeout

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