AD9551SLASHPCBZ datasheet(34/40 Pages) AD

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AD9551

Rev. B | Page 34 of 40

Output PLL Control (Register 0x11 to Register 0x19)

Table 26.

Address

Bit

Bit Name

Description

0x11

[7:0]

8-bit integer divide value for the output SDM. Default is 0x00.

Note that operational limitations impose a lower boundary of 64 (0x40) on N.

0x12

[7:0]

MOD

Bits[19:12] of the 20-bit modulus of the output SDM.

0x13

[7:0]

MOD

Bits[11:4] of the 20-bit modulus of the output SDM.

0x14

[7:4]

MOD

Bits[3:0] of the 20-bit modulus of the output SDM.

Default is MOD = 1000 0000 0000 0000 0000 (524,288).

Enable SPI control of

output frequency

Controls output frequency functionality.

0 = output frequency defined by the Y[3:0] pins (default).

1 = contents of Register 0x11 to Register 0x17 define output frequency via N, MOD, and FRAC.

Bypass output SDM

Controls bypassing of the output SDM.

0 = allow integer-plus-fractional division (default).

1 = allow only integer division.

Disable output SDM

Controls the output SDM internal clocks.

0 = normal operation (SDM clocks active) (default).

1 = SDM disabled (SDM clocks stopped).

Reset output PLL

Controls initialization of the output PLL.

0 = normal operation (default).

1 = resets the counters and logic associated with the output PLL but does not affect the

output dividers.

0x15

[7:0]

FRAC

Bits[19:12] of the 20-bit fractional part of the output SDM.

0x16

[7:0]

FRAC

Bits[11:4] of the 20-bit fractional part of the output SDM.

0x17

[7:4]

FRAC

Bits[3:0] of the 20-bit fractional part of the output SDM.

Default is FRAC = 0010 0000 0000 0000 0000 (131,072).

Enable OUTPUT PLL

LOCKED pin as test port

Controls functionality of the OUTPUT PLL LOCKED pin (Pin 26).

0 = OUTPUT PLL LOCKED pin indicates status of PLL lock detector (default).

1 = OUTPUT PLL LOCKED pin indicates the signal defined by Bits[2:1].

[2:1]

Test mux control

Selects test mux output.

00 = front end test clock (default).

01 = PFD up divide-by-2.

10 = PFD down divide-by-2.

11 = PLL feedback divide-by-2.

These bits are ineffective unless Bit 3 = 1.

P1 divider

Bit 5 of the 6-bit P1 divider for OUT1.

0x18

[7:3]

P1 divider

Bits[4:0] of the 6-bit P1 divider for OUT1 (1 ≤ P1 ≤ 63). Do not set these bits to 000000. Default is

P1 = 100000 (32). The P1 bits are ineffective unless Register 0x19[7] = 1.

[2:0]

P0 divider

Bits[2:0] of the 3-bit P0 divider for OUT1. The P0 divide value is as follows:

000 = 4 (default).

001 = 5.

010 = 6.

011 = 7.

100 = 8.

101 = 9.

110 = 10.

111 = 11.

The P0 bits are ineffective unless Register 0x19[7] = 1.

0x19

Enable SPI control of

OUT1 dividers

Controls functionality of OUT1 dividers.

0 = OUT1 dividers defined by the Y[3:0] pins (default).

1 = contents of Register 0x17 and Register 0x18 define OUT1 dividers (P0 and P1).

Enable SPI control of

OUT2 divider

Controls functionality of OUT2 divider.

0 = OUT2 divider defined by the Y[3:0] pins (P2 = 1) (default).

1 = contents of Bits[5:0] define P2.

[5:0]

P2 divider

Bits[5:0] of the 6-bit P2 divider for OUT2 (1 ≤ P2 ≤ 63). Do not set these bits to 000000. Default is

P2 = 100000 (32). The P2 bits are ineffective unless Register 0x19[6] = 1.

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