AD7985

Rev. 0 | Page 19 of 28

CS MODE, 3-WIRE WITHOUT BUSY INDICATOR

This mode is usually used when a single AD7985 is connected

to an SPI-compatible digital host. The connection diagram is

shown in Figure 26, and the corresponding timing is given in

Figure 27.

With SDI tied to VIO, a rising edge on CNV initiates a con-

version, selects CS mode, and forces SDO to high impedance.

When a conversion is initiated, it continues until completion,

irrespective of the state of CNV. This can be useful, for example,

to bring CNV low to select other SPI devices, such as analog

multiplexers; however, CNV must be returned high before the

minimum conversion time elapses and then held high for the

maximum possible conversion time to avoid the generation of

the busy signal indicator.

When the conversion is complete, the AD7985 enters the

acquisition phase and powers down. When CNV goes low, the

MSB is output onto SDO. The remaining data bits are clocked

by subsequent SCK falling edges. The data is valid on both SCK

edges. Although the rising edge can be used to capture the data,

a digital host using the SCK falling edge allows a faster reading

SCK falling edge or when CNV goes high (whichever occurs

first), SDO returns to high impedance.

AD7985

SDI

SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

VIO

Figure 26. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)

ACQUISITION (n)

ACQUISITION

(n + 1)

ACQUISITION

(n – 1)

1

2

BEGIN DATA (n – 1)

CONVERSION (n)

END DATA (n – 1)

SCK

CNV

SDO

14

15

CONVERSION (n – 1)

END DATA (n – 2)

0

(I/O QUIET

TIME)

(I/O QUIET

TIME)

16

14

15

16

115

14

13

2

0

1

2

SDI = 1

>

(I/O QUIET

TIME)

Figure 27. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)