AD7780

Rev. A | Page 7 of 16

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AD7780

TOP VIEW

(Not to Scale)

NC = NO CONNECT

1

2

3

4

5

6

7

8

SCLK

DOUT/RDY

NC

AIN(–)

AIN(+)

GAIN

NC

REFIN(+)

16

15

14

13

12

11

10

9

FILTER

PDRST

BPDSW

REFIN(–)

GND

NC

FILTER

14

PDRST

13

12

11

GND

10

BPDSW

9

REFIN(–)

8

AD7780

TOP VIEW

(Not to Scale)

NC = NO CONNECT

Figure 6. SOIC Pin Configuration

Figure 7. TSSOP Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

SOIC

TSSOP

Mnemonic

Description

1

2

SCLK

Serial Clock Input. This serial clock input is for data transfers from the ADC. The SCLK pin has a Schmitt-

triggered input. The serial clock can be active only when transferring data from the AD7780. The data

from the AD7780 can be read as a continuous 32-bit word. Alternatively, SCLK can be noncontinuous

during the data transfer, with the information being transmitted from the ADC in smaller data batches.

2

3

DOUT/RDY

Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose: as a data ready pin, going low to

indicate the completion of a conversion, and as a serial data output pin to access the data register of the

ADC. Eight status bits accompany each data read (see

). The DOUT/

Figure 22

RDY falling edge can be used

as an interrupt to a processor, indicating that new data is available. If the data is not read after the conver-

sion, the pin goes high before the next update occurs. The serial interface is reset each time that a conversion is

available. Therefore, the user must ensure that any conversions being transmitted are completed before

the next conversion is available.

3

1, 4, 16

NC

No Connect. This pin can be left floating.

4

5

GAIN

Gain Select Pin. When GAIN is low, the gain is set to 128. When GAIN is high, the gain is set to 1.

5

6

AIN(+)

Analog Input. AIN(+) is the positive terminal of the differential analog input pair, AIN(+)/AIN(−).

6

7

AIN(−)

Analog Input. AIN(−) is the negative terminal of the differential analog input pair, AIN(+)/AIN(−).

7

8

REFIN(+)

Positive Reference Input. An external reference can be applied between REFIN(+) and REFIN(−). The nomi-

8

9

REFIN(−)

Negative Reference Input.

9

10

BPDSW

Bridge Power-Down Switch to GND. When PDRST is high, the bridge power-down switch is closed. When

PDRST is low, the switch is opened.

10

11

GND

Ground Reference Point.

11

12

Supply Voltage, 2.7 V to 5.25 V.

12

13

Digital Interface Supply Voltage. The logic levels for the serial interface pins and the digital control pins

13

14

PDRST

Power-Down/Reset. When this pin is low, the ADC is placed in power-down mode, and the low-side power

switch is opened. All the logic on the chip is reset, and the DOUT/RDY pin is tristated. When PDRST is high,

the ADC is taken out of power-down mode. The on-chip clock powers up and settles, and the ADC

continuously converts. In addition, the low-side power switch is closed. The internal clock requires

approximately 1 ms to power up.

14

15

FILTER

Filter Select. When FILTER is low, the fast settling filter is selected. The update rate is set to 16.7 Hz, which

gives a filter settling time of 120 ms. When FILTER is high, the high rejection filter is selected. The update

rate is set to 10 Hz, which gives a filter settling time of 300 ms. With this filter, the stop-band (higher than