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Specifies the type of burst (sequential or interleaved), M4-M6

specify the CAS latency, M7 and M8 specify the operating

mode, M9 specifies the WRITE BURST mode and M10,

M11 are reserved for future use. Address A12 (M12) is

undefined but should be driven LOW during loading of the

MODE REGISTER.

The MODE REGISTER must be loaded when all banks are

idle, and the controller must wait the specified time before

initiating the subsequent operation. Violating either of these

requirements will result in unspecified operation.

Burst Length

READ and WRITE accesses to the SDRAM are burst

oriented, with the burst length being programmable. The

burst length determines the maximum number of column

locations that can be accessed for a given READ or WRITE

command. Burst lengths of 1,2,4 and 8 locations are available

for both the sequential and the interleaved burst types, and a

full page burst is available for the sequential burst mode. The

full-page burst is used in conjunction with the BURST

TERMINATE command to generate arbitrary burst lengths.

Reserved states should not be used, aas unknown operation or

incompatibility with future versions may result.

When a READ or WRITE command is issued, a block of

columns equal to the burst length is effectively selected. All

accesses for that burst will wrap within this block, meaning

that the burst will wrap within the block if a boundary is

reached. The block is uniquely selected by A2-A8 (each x16)

when the burst length is set to four; and by A3-A8 (each x16)

when the burst length is set to eight. The remaining (least

significant) address bit(s) is (are) used to select the starting

location within the block. Full-page bursts wrap within the

page if the boundary is reached.

CAS Latency

The CAS latency is the delay, in clock cycles, between the

registration of a READ command and the availability of first

valid data presented on the Output bus (DQ0-DQ79). The

latency can be set to two or three clocks.

If a READ command is registered at clock edge n, and the

latency is m clocks, the data will be available by clock edge

N + m. The DQs will start driving as a result of the clock

edge one cycle earlier (n + m - 1), and provided that the

relevant access times are met, the data will be valid by

clock edge n + m. For example, assuming that the clock

cycle time is such that all relevant access times are met, If

a READ command is registered at T0 and the latency is

programmed to two clocks, the DQs will be valid by T2.

Reserved states should not be used as unknown operation

or incompatibility with future versions may result.

Operating Mode

The normal operating mode is selected by setting M7 and

M8 to zero; the other combinations of values for M7 and

M8 are reserved for future use and/or test modes. The

programmed burst length applies to both READ and

WRITE bursts.

Test Modes and reserved states should not be used

because unknown operation or incompatibility with future

version may result.

Write Burst Mode

When M9=0, the burst length programmed via M0-M2

applies to both READ and WRITE bursts; when M9=1,

the programmed burst length applies to READ bursts, but

WRITE accesses are single-location (non-burst) accesses.

Command Inhibit

The COMMAND INHIBIT function prevents new

commands from being executed by the SDRAM,

regardless of whether the CLK signal is enabled. The

SDRAM is effectively deselected. Operations already in

progress are not affected.

No Operation (NOP)

The NO OPERATION (NOP) command is used to

perform a NOP to an SDRAM which is selected (CS\ is

LOW). This prevents unwanted commands from being

registered during IDLE or WAIT states. Operations

already in progress are not affected.

AS4SD16M72PBG-s/IT,ET,XT

16M x 72, SDR SDRAM, 3.3v Core/ 3.3v IO