CS8422 datasheet(56/82 Pages) CIRRUS

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DS692PP2

CS8422

SORES2[1:0] - Resolution of the output data on SDOUT

00 - 24-bit resolution.

01 - 20-bit resolution.

10 - 18-bit resolution.

11 - 16-bit resolution

SOFSEL2[1:0] - Format of the output data on SDOUT

00 - Left-Justified

01 - I²S

10 - Right-Justified (Master mode only)

11 - AES3 Direct. Direct copy of the received NRZ data from the AES3 receiver including C, U, and V bits.

The time slot occupied by the Z bit is used to indicate the location of the block start. Only valid if serial port

source is the AES3-compatible receiver.

11.14 Receiver Error Unmasking (0Eh)

RECEIVER ERROR MASK[7:0]

The bits[7:0] in this register serve as masks for the corresponding bits of the Receiver Error Register. If a

mask bit is set to 1, the error is unmasked, meaning that its occurrence will appear in the receiver error reg-

ister, will affect RERR[6:0], will affect the RERR interrupt, and will affect the current audio sample according

to the status of the HOLD bit. If a mask bit is set to 0, the error is masked, meaning that its occurrence will

not appear in the receiver error register, will not affect the RERR pin, will not affect the RERR interrupt, and

will not affect the current audio sample. The ACTIVE, CCRC, and QCRC bits behave differently from the

other bits: they do not affect the current audio sample even when unmasked. If QCRC, CCRC, CONF, BIP,

or PARM are unmasked, and RERRM in register 0Fh is unmasked, then RERR[1:0] should be set to “Rising

Edge Active” in the Interrupt Mode register (register 10h). This register defaults to 00h.

11.15 Interrupt Unmasking (0Fh)

The bits of this register serve as a mask for the Interrupt Status register. If a mask bit is set to 1, the error

is unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set

0010

128

0011

192

0100

256

128

0101

384

0110

512

128

0111

768

1000

1024

128

543

210

ACTIVEM

QCRCM

CCRCM

UNLOCKM

CONFM

BIPM

PARM

000

432

PCCHM

OSLIPM

DETCM

CCHM

RERRM

QCHM

FCHM

SRC_UNLOCKM

000

Table 10. OSCLK2/OLRCK2 Ratios and SOSF1 Settings

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