CS5566

6

DS806PP2

5/4/09

SWITCHING CHARACTERISTICS

VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V Low; Logic 1 = VD+ = High; CL = 15 pF.

8.

BP/UP can be changed coincident CONV falling. BP/UP must remain stable until RDY falls.

9.

If CONV is held low continuously, conversions occur every 1600 MCLK cycles.

If RDY is tied to CONV, conversions will occur every 1602 MCLKs.

If CONV is operated asynchronously to MCLK, a conversion may take up to 1604 MCLKs.

RDY falls at the end of conversion.

10.

RDY will fall when the device is fully operational when coming out of sleep mode.

Figure 1. Converter Status (Not to scale)

Parameter

Symbol

Min

Typ

Max

Unit

Master Clock Frequency

Internal Oscillator

External Clock

XIN

6

0.5

7

8

8

8.1

MHz

MHz

Master Clock Duty Cycle

40

-

60

%

Reset

RST Low Time

1-

-

µs

RST rising to RDY falling

Internal Oscillator

External Clock

-

-

240

3084

-

-

µs

MCLKs

Conversion

CONV Pulse Width

4-

-

MCLKs

BP/UP setup to CONV falling

(Note 8)

0-

-

ns

CONV low to start of conversion

-

1182

1186

MCLKs

Perform Single Conversion (CONV high before RDY falling)

20

-

-

MCLKs

Conversion Time

(Note 9)

Start of Conversion to RDY falling

-

-

1604

MCLKs

Sleep Mode

SLEEP low to low-power state

SLEEP high to device active (Note 10)

-

-

50

3083

-

-

µs

MCLKs

1182 - 1186 MCLKs

Converter

Status

CONVERT

RDY

IDLE

IDLE

CONVERT

SDO

ACTIVE

354 + 64 MCLKs

1600 - 1604 MCLKs