CS485xx Family Data Sheet

32-bit Audio Decoder DSP Family

DS734F3

Copyright 2009 Cirrus Logic, Inc.

15

CONFIDENTIAL

Figure 4. Serial Control Port - SPI Master Mode Timing

Parameter

Symbol

Min

Typical

Max

Units

maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin

should be implemented to prevent overflow of the input data buffer.

-

400

kHz

SCP_CLK low time

1.25

-

µs

SCP_CLK high time

1.25

-

µs

SCP_SCK rising to SCP_SDA rising or falling for

START or STOP condition

1.25

µs

START condition to SCP_CLK falling

1.25

-

µs

SCP_CLK falling to STOP condition

2.5

-

µs

Bus free time between STOP and START conditions

3-

µs

Setup time SCP_SDA input valid to SCP_CLK rising

100

ns

Hold time SCP_SDA input after SCP_CLK falling

20

-

ns

SCP_CLK low to SCP_SDA out valid

-18

ns

SCP_CLK falling to SCP_IRQ# rising

ns

NAK condition to SCP_IRQ# low

ns

SCP_CLK rising to SCB_BSY# low

ns

EE_CS#

SCP_CLK

SCP_MISO

SCP_MOSI

0

12

67

0

56

7

A6

A5

A0

R/W

MSB

LSB

MSB

LSB