CS2000-CP_09 datasheet(16/36 Pages) CIRRUS

16 / 36 page

CS2000-CP

DS761F1

Regardless of the setting of the ClkSkipEn bit the PLL output will continue for 223 SysClk cycles (466 ms

to 1048 ms) after CLK_IN is removed (see Figure 13). This is true as long as CLK_IN does not glitch or

have an effective change in period as the clock source is removed, otherwise the PLL will interpret this as

a change in frequency causing clock skipping and the 223 SysClk cycle time-out to be bypassed and the

PLL to immediately unlock. If the prior conditions are met while CLK_IN is removed and 223 SysClk cycles

pass, the PLL will unlock and the PLL_OUT state will be determined by the ClkOutUnl bit; See “PLL Clock

Output” on page 23. If CLK_IN is re-applied after such time, the PLL will remain unlocked for the specified

time listed in the “AC Electrical Characteristics” on page 8 after which lock will be acquired and the PLL

output will resume.

If it is expected that CLK_IN will be removed and then reapplied within 223 SysClk cycles but later than

tCS, the ClkSkipEn bit should be disabled. If it is not disabled, the device will behave as shown in

Figure 14; note that the lower figure shows that the PLL output frequency may change and be incorrect

without an indication of an unlock condition.

Figure 13. CLK_IN removed for > 223 SysClk cycles

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn=0 or 1

ClkOutUnl=0

Lock Time

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn=0 or 1

ClkOutUnl=1

Lock Time

= invalid clocks

223 SysClk cycles

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn=0 or 1

ClkOutUnl=0

Lock Time

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn=0 or 1

ClkOutUnl=1

Lock Time

tCS

= invalid clocks

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn= 1

ClkOutUnl=1

Lock Time

tCS

= invalid clocks

223 SysClk cycles

Figure 14. CLK_IN removed for < 223 SysClk cycles but > tCS

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